endif()
endif()
-option(LLVM_BUILD_GLOBAL_ISEL "Experimental: Build GlobalISel" ON)
-if(LLVM_BUILD_GLOBAL_ISEL)
- add_definitions(-DLLVM_BUILD_GLOBAL_ISEL)
-endif()
-
option(LLVM_ENABLE_DAGISEL_COV "Debug: Prints tablegen patterns that were used for selecting" OFF)
# Add path for custom modules
-# List of all GlobalISel files.
-set(GLOBAL_ISEL_FILES
- CallLowering.cpp
- IRTranslator.cpp
- InstructionSelect.cpp
- InstructionSelector.cpp
- MachineIRBuilder.cpp
- LegalizerHelper.cpp
- Legalizer.cpp
- LegalizerInfo.cpp
- Localizer.cpp
- RegBankSelect.cpp
- RegisterBank.cpp
- RegisterBankInfo.cpp
- Utils.cpp
- )
-
-# Add GlobalISel files to the dependencies if the user wants to build it.
-if(LLVM_BUILD_GLOBAL_ISEL)
- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
-else()
- set(GLOBAL_ISEL_BUILD_FILES"")
- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
-endif()
-
# In LLVMBuild.txt files, it is not possible to mark a dependency to a
# library as optional. So instead, generate an empty library if we did
# not ask for it.
add_llvm_library(LLVMGlobalISel
- ${GLOBAL_ISEL_BUILD_FILES}
+ CallLowering.cpp
GlobalISel.cpp
+ IRTranslator.cpp
+ InstructionSelect.cpp
+ InstructionSelector.cpp
+ LegalizerHelper.cpp
+ Legalizer.cpp
+ LegalizerInfo.cpp
+ Localizer.cpp
+ MachineIRBuilder.cpp
+ RegBankSelect.cpp
+ RegisterBank.cpp
+ RegisterBankInfo.cpp
+ Utils.cpp
DEPENDS
intrinsics_gen
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-
-void llvm::initializeGlobalISel(PassRegistry &Registry) {
-}
-
-#else
-
void llvm::initializeGlobalISel(PassRegistry &Registry) {
initializeIRTranslatorPass(Registry);
initializeLegalizerPass(Registry);
initializeRegBankSelectPass(Registry);
initializeInstructionSelectPass(Registry);
}
-#endif // LLVM_BUILD_GLOBAL_ISEL
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "This shouldn't be built without GISel"
-#endif
-
AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
: CallLowering(&TLI) {}
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
namespace llvm {
RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
namespace {
#define GET_GLOBALISEL_PREDICATE_BITSET
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
AArch64LegalizerInfo::AArch64LegalizerInfo() {
using namespace TargetOpcode;
const LLT p0 = LLT::pointer(0, 64);
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
: AArch64GenRegisterBankInfo() {
static bool AlreadyInit = false;
#include "AArch64PBQPRegAlloc.h"
#include "AArch64TargetMachine.h"
-#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "AArch64CallLowering.h"
#include "AArch64LegalizerInfo.h"
#include "AArch64RegisterBankInfo.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
-#endif
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/Support/TargetRegistry.h"
}
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
namespace {
struct AArch64GISelActualAccessor : public GISelAccessor {
};
} // end anonymous namespace
-#endif
AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
TLInfo(TM, *this), GISel() {
-#ifndef LLVM_BUILD_GLOBAL_ISEL
- GISelAccessor *AArch64GISel = new GISelAccessor();
-#else
AArch64GISelActualAccessor *AArch64GISel = new AArch64GISelActualAccessor();
AArch64GISel->CallLoweringInfo.reset(
new AArch64CallLowering(*getTargetLowering()));
*static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
AArch64GISel->RegBankInfo.reset(RBI);
-#endif
setGISelAccessor(*AArch64GISel);
}
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool addIRTranslator() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
void addPreGlobalInstructionSelect() override;
bool addGlobalInstructionSelect() override;
-#endif
bool addILPOpts() override;
void addPreRegAlloc() override;
void addPostRegAlloc() override;
return false;
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool AArch64PassConfig::addIRTranslator() {
addPass(new IRTranslator());
return false;
addPass(new InstructionSelect());
return false;
}
-#endif
bool AArch64PassConfig::isGlobalISelEnabled() const {
return TM->getOptLevel() <= EnableGlobalISelAtO;
tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
-if(LLVM_BUILD_GLOBAL_ISEL)
- tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
- tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
-endif()
+tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
+tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
add_public_tablegen_target(AArch64CommonTableGen)
-# List of all GlobalISel files.
-set(GLOBAL_ISEL_FILES
- AArch64CallLowering.cpp
- AArch64InstructionSelector.cpp
- AArch64LegalizerInfo.cpp
- AArch64RegisterBankInfo.cpp
- )
-
-# Add GlobalISel files to the dependencies if the user wants to build it.
-if(LLVM_BUILD_GLOBAL_ISEL)
- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
-else()
- set(GLOBAL_ISEL_BUILD_FILES"")
- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
-endif()
-
-
add_llvm_target(AArch64CodeGen
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
+ AArch64CallLowering.cpp
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64CondBrTuning.cpp
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp
AArch64InstrInfo.cpp
+ AArch64InstructionSelector.cpp
+ AArch64LegalizerInfo.cpp
AArch64LoadStoreOptimizer.cpp
AArch64MacroFusion.cpp
AArch64MCInstLower.cpp
AArch64PromoteConstant.cpp
AArch64PBQPRegAlloc.cpp
+ AArch64RegisterBankInfo.cpp
AArch64RegisterInfo.cpp
AArch64SelectionDAGInfo.cpp
AArch64StorePairSuppress.cpp
AArch64TargetObjectFile.cpp
AArch64TargetTransformInfo.cpp
AArch64VectorByElementOpt.cpp
- ${GLOBAL_ISEL_BUILD_FILES}
DEPENDS
intrinsics_gen
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "This shouldn't be built without GISel"
-#endif
-
AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
: CallLowering(&TLI), AMDGPUASI(TLI.getAMDGPUAS()) {
}
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
namespace llvm {
namespace AMDGPU {
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
using namespace TargetOpcode;
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
: AMDGPUGenRegisterBankInfo(),
TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
#include "AMDGPUSubtarget.h"
#include "AMDGPU.h"
#include "AMDGPUTargetMachine.h"
-#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "AMDGPUCallLowering.h"
#include "AMDGPUInstructionSelector.h"
#include "AMDGPULegalizerInfo.h"
#include "AMDGPURegisterBankInfo.h"
-#endif
#include "SIMachineFunctionInfo.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/CodeGen/MachineScheduler.h"
return *this;
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
namespace {
struct SIGISelActualAccessor : public GISelAccessor {
};
} // end anonymous namespace
-#endif
AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
const TargetMachine &TM)
: AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this),
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
TLInfo(TM, *this) {
-#ifndef LLVM_BUILD_GLOBAL_ISEL
- GISelAccessor *GISel = new GISelAccessor();
-#else
SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
GISel->CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));
GISel->Legalizer.reset(new AMDGPULegalizerInfo());
GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));
GISel->InstSelector.reset(new AMDGPUInstructionSelector(
*this, *static_cast<AMDGPURegisterBankInfo *>(GISel->RegBankInfo.get())));
-#endif
setGISelAccessor(*GISel);
}
void addMachineSSAOptimization() override;
bool addILPOpts() override;
bool addInstSelector() override;
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool addIRTranslator() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override;
-#endif
void addFastRegAlloc(FunctionPass *RegAllocPass) override;
void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
void addPreRegAlloc() override;
return false;
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool GCNPassConfig::addIRTranslator() {
addPass(new IRTranslator());
return false;
return false;
}
-#endif
-
void GCNPassConfig::addPreRegAlloc() {
if (LateCFGStructurize) {
addPass(createAMDGPUMachineCFGStructurizerPass());
tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
-if(LLVM_BUILD_GLOBAL_ISEL)
- tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
-endif()
+tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
add_public_tablegen_target(AMDGPUCommonTableGen)
-# List of all GlobalISel files.
-set(GLOBAL_ISEL_FILES
- AMDGPUCallLowering.cpp
- AMDGPUInstructionSelector.cpp
- AMDGPULegalizerInfo.cpp
- AMDGPURegisterBankInfo.cpp
- )
-
-# Add GlobalISel files to the dependencies if the user wants to build it.
-if(LLVM_BUILD_GLOBAL_ISEL)
- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
-else()
- set(GLOBAL_ISEL_BUILD_FILES"")
- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
-endif()
-
-
add_llvm_target(AMDGPUCodeGen
AMDILCFGStructurizer.cpp
AMDGPUAliasAnalysis.cpp
AMDGPUAnnotateKernelFeatures.cpp
AMDGPUAnnotateUniformValues.cpp
AMDGPUAsmPrinter.cpp
+ AMDGPUCallLowering.cpp
AMDGPUCodeGenPrepare.cpp
AMDGPUFrameLowering.cpp
+ AMDGPULegalizerInfo.cpp
AMDGPUTargetObjectFile.cpp
+ AMDGPUInstructionSelector.cpp
AMDGPUIntrinsicInfo.cpp
AMDGPUISelDAGToDAG.cpp
AMDGPULowerIntrinsics.cpp
AMDGPUInstrInfo.cpp
AMDGPUPromoteAlloca.cpp
AMDGPURegAsmNames.inc.cpp
+ AMDGPURegisterBankInfo.cpp
AMDGPURegisterInfo.cpp
AMDGPURewriteOutArguments.cpp
AMDGPUUnifyDivergentExitNodes.cpp
GCNIterativeScheduler.cpp
GCNMinRegStrategy.cpp
GCNRegPressure.cpp
- ${GLOBAL_ISEL_BUILD_FILES}
)
add_subdirectory(AsmParser)
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "This shouldn't be built without GISel"
-#endif
-
ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
: CallLowering(&TLI) {}
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
namespace {
#define GET_GLOBALISEL_PREDICATE_BITSET
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
static bool AEABI(const ARMSubtarget &ST) {
return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
}
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
// FIXME: TableGen this.
// If it grows too much and TableGen still isn't ready to do the job, extract it
// into an ARMGenRegisterBankInfo.def (similar to AArch64).
#include "ARM.h"
-#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "ARMCallLowering.h"
#include "ARMLegalizerInfo.h"
#include "ARMRegisterBankInfo.h"
-#endif
#include "ARMSubtarget.h"
#include "ARMFrameLowering.h"
#include "ARMInstrInfo.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
-#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
-#endif
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
return new ARMFrameLowering(STI);
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
namespace {
struct ARMGISelActualAccessor : public GISelAccessor {
};
} // end anonymous namespace
-#endif
ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
assert((isThumb() || hasARMOps()) &&
"Target must either be thumb or support ARM operations!");
-#ifndef LLVM_BUILD_GLOBAL_ISEL
- GISelAccessor *GISel = new GISelAccessor();
-#else
ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
GISel->Legalizer.reset(new ARMLegalizerInfo(*this));
*static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
GISel->RegBankInfo.reset(RBI);
-#endif
setGISelAccessor(*GISel);
}
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool addIRTranslator() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override;
-#endif
void addPreRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
return false;
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool ARMPassConfig::addIRTranslator() {
addPass(new IRTranslator());
return false;
addPass(new InstructionSelect());
return false;
}
-#endif
void ARMPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None) {
set(LLVM_TARGET_DEFINITIONS ARM.td)
-if(LLVM_BUILD_GLOBAL_ISEL)
- tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
- tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
-endif()
+tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables)
add_public_tablegen_target(ARMCommonTableGen)
-# Add GlobalISel files if the user wants to build it.
-set(GLOBAL_ISEL_FILES
- ARMCallLowering.cpp
- ARMInstructionSelector.cpp
- ARMLegalizerInfo.cpp
- ARMRegisterBankInfo.cpp
- )
-
-if(LLVM_BUILD_GLOBAL_ISEL)
- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
-else()
- set(GLOBAL_ISEL_BUILD_FILES "")
- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
-endif()
-
add_llvm_target(ARMCodeGen
A15SDOptimizer.cpp
ARMAsmPrinter.cpp
ARMBaseInstrInfo.cpp
ARMBaseRegisterInfo.cpp
+ ARMCallLowering.cpp
ARMConstantIslandPass.cpp
ARMConstantPoolValue.cpp
ARMExpandPseudoInsts.cpp
ARMFastISel.cpp
ARMFrameLowering.cpp
ARMHazardRecognizer.cpp
+ ARMInstructionSelector.cpp
ARMISelDAGToDAG.cpp
ARMISelLowering.cpp
ARMInstrInfo.cpp
+ ARMLegalizerInfo.cpp
ARMLoadStoreOptimizer.cpp
ARMMCInstLower.cpp
ARMMachineFunctionInfo.cpp
ARMMacroFusion.cpp
ARMRegisterInfo.cpp
ARMOptimizeBarriersPass.cpp
+ ARMRegisterBankInfo.cpp
ARMSelectionDAGInfo.cpp
ARMSubtarget.cpp
ARMTargetMachine.cpp
Thumb2InstrInfo.cpp
Thumb2SizeReduction.cpp
ARMComputeBlockSize.cpp
- ${GLOBAL_ISEL_BUILD_FILES}
)
add_subdirectory(TargetInfo)
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)
-if(LLVM_BUILD_GLOBAL_ISEL)
- tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
- tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
-endif()
+tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
+tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
add_public_tablegen_target(X86CommonTableGen)
-# Add GlobalISel files if the build option was enabled.
-set(GLOBAL_ISEL_FILES
- X86CallLowering.cpp
- X86LegalizerInfo.cpp
- X86RegisterBankInfo.cpp
- X86InstructionSelector.cpp
- )
-
-if(LLVM_BUILD_GLOBAL_ISEL)
- set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
-else()
- set(GLOBAL_ISEL_BUILD_FILES "")
- set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
-endif()
-
-
set(sources
X86AsmPrinter.cpp
X86CallFrameOptimization.cpp
+ X86CallLowering.cpp
X86CmovConversion.cpp
X86ExpandPseudo.cpp
X86FastISel.cpp
X86FixupSetCC.cpp
X86FloatingPoint.cpp
X86FrameLowering.cpp
+ X86InstructionSelector.cpp
X86ISelDAGToDAG.cpp
X86ISelLowering.cpp
X86InterleavedAccess.cpp
X86InstrFMA3Info.cpp
X86InstrInfo.cpp
X86EvexToVex.cpp
+ X86LegalizerInfo.cpp
X86MCInstLower.cpp
X86MachineFunctionInfo.cpp
X86MacroFusion.cpp
X86OptimizeLEAs.cpp
X86PadShortFunction.cpp
+ X86RegisterBankInfo.cpp
X86RegisterInfo.cpp
X86SelectionDAGInfo.cpp
X86ShuffleDecodeConstantPool.cpp
X86WinAllocaExpander.cpp
X86WinEHState.cpp
X86CallingConv.cpp
- ${GLOBAL_ISEL_BUILD_FILES}
)
add_llvm_target(X86CodeGen ${sources})
#include "X86GenCallingConv.inc"
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "This shouldn't be built without GISel"
-#endif
-
X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
: CallLowering(&TLI) {}
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
#ifdef GET_TARGET_REGBANK_INFO_IMPL
RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
using namespace llvm;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
namespace {
#define GET_GLOBALISEL_PREDICATE_BITSET
using namespace llvm;
using namespace TargetOpcode;
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
const X86TargetMachine &TM)
: Subtarget(STI), TM(TM) {
#define GET_TARGET_REGBANK_INFO_IMPL
#include "X86GenRegisterBankInfo.def"
-#ifndef LLVM_BUILD_GLOBAL_ISEL
-#error "You shouldn't build this"
-#endif
-
X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)
: X86GenRegisterBankInfo() {
#include "X86.h"
-#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "X86CallLowering.h"
#include "X86LegalizerInfo.h"
#include "X86RegisterBankInfo.h"
-#endif
#include "X86Subtarget.h"
#include "MCTargetDesc/X86BaseInfo.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/Triple.h"
-#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
-#endif
#include "llvm/IR/Attributes.h"
#include "llvm/IR/ConstantRange.h"
#include "llvm/IR/Function.h"
return *this;
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
namespace {
struct X86GISelActualAccessor : public GISelAccessor {
};
} // end anonymous namespace
-#endif
X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
const X86TargetMachine &TM,
setPICStyle(PICStyles::StubPIC);
else if (isTargetELF())
setPICStyle(PICStyles::GOT);
-#ifndef LLVM_BUILD_GLOBAL_ISEL
- GISelAccessor *GISel = new GISelAccessor();
-#else
X86GISelActualAccessor *GISel = new X86GISelActualAccessor();
GISel->CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
GISel->RegBankInfo.reset(RBI);
GISel->InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
-#endif
setGISelAccessor(*GISel);
}
void addIRPasses() override;
bool addInstSelector() override;
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool addIRTranslator() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override;
-#endif
bool addILPOpts() override;
bool addPreISel() override;
void addPreRegAlloc() override;
return false;
}
-#ifdef LLVM_BUILD_GLOBAL_ISEL
bool X86PassConfig::addIRTranslator() {
addPass(new IRTranslator());
return false;
addPass(new InstructionSelect());
return false;
}
-#endif
bool X86PassConfig::addILPOpts() {
addPass(&EarlyIfConverterID);
set(LLVM_BUILD_SYSTEM cmake)
set(LLVM_HAS_RTTI ${LLVM_CONFIG_HAS_RTTI})
set(LLVM_DYLIB_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}${LLVM_VERSION_SUFFIX}")
-if(LLVM_BUILD_GLOBAL_ISEL)
- set(LLVM_HAS_GLOBAL_ISEL "ON")
-else()
- set(LLVM_HAS_GLOBAL_ISEL "OFF")
-endif()
+set(LLVM_HAS_GLOBAL_ISEL "ON")
# Use the C++ link flags, since they should be a superset of C link flags.
set(LLVM_LDFLAGS "${CMAKE_CXX_LINK_FLAGS}")
CodeGen
)
-if(LLVM_BUILD_GLOBAL_ISEL)
- add_llvm_unittest(GlobalISelTests
- LegalizerInfoTest.cpp
- )
-endif()
+add_llvm_unittest(GlobalISelTests
+ LegalizerInfoTest.cpp
+ )
projects / llvm / commitdiff