[SystemZ] Use tablegen loops in SchedModels

NFC changes to make scheduler TableGen files more readable, by using loops
instead of a lot of similar defs with just e.g. a latency value that changes.

https://reviews.llvm.org/D49598
Review: Ulrich Weigand, Javed Abshar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337909 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZSchedule.td b/lib/Target/SystemZ/SystemZSchedule.td
index 7cdb774cd4a0812cd46edce4f1568f269b0d5eee..385a94b5d6a9f8b1c77b75fb563bb19967ee9ad0 100644 (file)
--- a/lib/Target/SystemZ/SystemZSchedule.td
+++ b/lib/Target/SystemZ/SystemZSchedule.td
@@ -22,96 +22,43 @@ def EndGroup   : SchedWrite;
 def LSULatency : SchedWrite;
 
 // Operand WriteLatencies.
-def WLat1 : SchedWrite;
-def WLat2 : SchedWrite;
-def WLat3 : SchedWrite;
-def WLat4 : SchedWrite;
-def WLat5 : SchedWrite;
-def WLat6 : SchedWrite;
-def WLat7 : SchedWrite;
-def WLat8 : SchedWrite;
-def WLat9 : SchedWrite;
-def WLat10 : SchedWrite;
-def WLat11 : SchedWrite;
-def WLat12 : SchedWrite;
-def WLat15 : SchedWrite;
-def WLat16 : SchedWrite;
-def WLat20 : SchedWrite;
-def WLat26 : SchedWrite;
-def WLat30 : SchedWrite;
+foreach L = 1 - 30 in def "WLat"#L : SchedWrite;
 
-def WLat1LSU : WriteSequence<[WLat1, LSULatency]>;
-def WLat2LSU : WriteSequence<[WLat2, LSULatency]>;
-def WLat3LSU : WriteSequence<[WLat3, LSULatency]>;
-def WLat4LSU : WriteSequence<[WLat4, LSULatency]>;
-def WLat6LSU : WriteSequence<[WLat6, LSULatency]>;
-def WLat5LSU : WriteSequence<[WLat5, LSULatency]>;
-def WLat7LSU : WriteSequence<[WLat7, LSULatency]>;
-def WLat8LSU : WriteSequence<[WLat8, LSULatency]>;
-def WLat11LSU : WriteSequence<[WLat11, LSULatency]>;
-def WLat16LSU : WriteSequence<[WLat16, LSULatency]>;
+foreach L = 1 - 16 in
+  def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
+                                      LSULatency]>;
 
 // ReadAdvances, used for the register operand next to a memory operand,
 // modelling that the register operand is needed later than the address
 // operands.
 def RegReadAdv : SchedRead;
 
-// Fixed-point units
-def FXa         : SchedWrite;
-def FXa2        : SchedWrite;
-def FXa3        : SchedWrite;
-def FXa4        : SchedWrite;
-def FXb         : SchedWrite;
-def FXb2        : SchedWrite;
-def FXb3        : SchedWrite;
-def FXb4        : SchedWrite;
-def FXb5        : SchedWrite;
-def FXU         : SchedWrite;
-def FXU2        : SchedWrite;
-def FXU3        : SchedWrite;
-def FXU4        : SchedWrite;
-def FXU5        : SchedWrite;
-def FXU6        : SchedWrite;
+foreach Num = ["", "2", "3", "4", "5", "6"] in {
+  // Fixed-point units
+  def "FXa"#Num : SchedWrite;
+  def "FXb"#Num : SchedWrite;
+  def "FXU"#Num : SchedWrite;
+  // Load/store unit
+  def "LSU"#Num : SchedWrite;
+  // Vector sub units (z13 and later)
+  def "VecBF"#Num : SchedWrite;
+  def "VecDF"#Num : SchedWrite;
+  def "VecDFX"#Num : SchedWrite;
+  def "VecMul"#Num : SchedWrite;
+  def "VecStr"#Num : SchedWrite;
+  def "VecXsPm"#Num : SchedWrite;
+  // Floating point unit (zEC12 and earlier)
+  def "FPU"#Num : SchedWrite;
+  def "DFU"#Num : SchedWrite;
+}
 
-// Load/store unit
-def LSU         : SchedWrite;
-def LSU2        : SchedWrite;
-def LSU3        : SchedWrite;
-def LSU4        : SchedWrite;
-def LSU5        : SchedWrite;
+def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
 
-// Floating point unit (zEC12 and earlier)
-def FPU  : SchedWrite;
-def FPU2 : SchedWrite;
-def FPU4 : SchedWrite;
-def DFU  : SchedWrite;
-def DFU2 : SchedWrite;
-def DFU4 : SchedWrite;
+def VBU : SchedWrite; // Virtual branching unit
 
-// Vector sub units (z13 and later)
-def VecBF     : SchedWrite;
-def VecBF2    : SchedWrite;
-def VecBF4    : SchedWrite;
-def VecDF     : SchedWrite;
-def VecDF2    : SchedWrite;
-def VecDF4    : SchedWrite;
-def VecDFX    : SchedWrite;
-def VecDFX2   : SchedWrite;
-def VecDFX4   : SchedWrite;
-def VecFPd    : SchedWrite; // Blocking BFP div/sqrt unit.
-def VecMul    : SchedWrite;
-def VecStr    : SchedWrite;
-def VecXsPm   : SchedWrite;
-def VecXsPm2  : SchedWrite;
-
-// Virtual branching unit
-def VBU       : SchedWrite;
-
-// Millicode
-def MCD       : SchedWrite;
+def MCD : SchedWrite; // Millicode
 
 include "SystemZScheduleZ14.td"
 include "SystemZScheduleZ13.td"
 include "SystemZScheduleZEC12.td"
 include "SystemZScheduleZ196.td"
-

diff --git a/lib/Target/SystemZ/SystemZScheduleZ13.td b/lib/Target/SystemZ/SystemZScheduleZ13.td
index b9c893597535cc586674085cfb8fd6a329c4cb4a..5d32232107af9ed8356fb00f89b9cec0361989fa 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -59,22 +59,8 @@ def : ReadAdvance<RegReadAdv, 4>;
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
 }
 
 // Execution units.
@@ -88,36 +74,30 @@ def Z13_MCD         : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXa,     [Z13_FXaUnit]>;
-  def : WriteRes<FXa2,    [Z13_FXaUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXa3,    [Z13_FXaUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXa4,    [Z13_FXaUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb,     [Z13_FXbUnit]>;
-  def : WriteRes<FXb2,    [Z13_FXbUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXb3,    [Z13_FXbUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXb4,    [Z13_FXbUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb5,    [Z13_FXbUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<LSU,     [Z13_LSUnit]>;
-  def : WriteRes<LSU2,    [Z13_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3,    [Z13_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU4,    [Z13_LSUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<LSU5,    [Z13_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<VecBF,   [Z13_VecUnit]>;
-  def : WriteRes<VecBF2,  [Z13_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecBF4,  [Z13_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDF,   [Z13_VecUnit]>;
-  def : WriteRes<VecDF2,  [Z13_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDF4,  [Z13_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDFX,  [Z13_VecUnit]>;
-  def : WriteRes<VecDFX2, [Z13_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDFX4, [Z13_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<FXa, [Z13_FXaUnit]>;
+  def : WriteRes<FXb, [Z13_FXbUnit]>;
+  def : WriteRes<LSU, [Z13_LSUnit]>;
+  def : WriteRes<VecBF,  [Z13_VecUnit]>;
+  def : WriteRes<VecDF,  [Z13_VecUnit]>;
+  def : WriteRes<VecDFX, [Z13_VecUnit]>;
   def : WriteRes<VecMul,  [Z13_VecUnit]>;
   def : WriteRes<VecStr,  [Z13_VecUnit]>;
   def : WriteRes<VecXsPm, [Z13_VecUnit]>;
-  def : WriteRes<VecXsPm2,[Z13_VecUnit]> { let ResourceCycles = [2]; }
-  // Virtual Branching Unit
-  def : WriteRes<VBU,     [Z13_VBUnit]>;
+  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
+  }}
+
+  def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
+
+  def : WriteRes<VBU,     [Z13_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z13_MCD]> { let NumMicroOps = 3;

diff --git a/lib/Target/SystemZ/SystemZScheduleZ14.td b/lib/Target/SystemZ/SystemZScheduleZ14.td
index 5b6b250587b8cd90e285a3a6d7976932b5c58b91..515f968e5091b7219c2d6bbe9cb1a72562bd2815 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -59,22 +59,8 @@ def : ReadAdvance<RegReadAdv, 4>;
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
 }
 
 // Execution units.
@@ -88,36 +74,30 @@ def Z14_MCD         : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXa,     [Z14_FXaUnit]>;
-  def : WriteRes<FXa2,    [Z14_FXaUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXa3,    [Z14_FXaUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXa4,    [Z14_FXaUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb,     [Z14_FXbUnit]>;
-  def : WriteRes<FXb2,    [Z14_FXbUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXb3,    [Z14_FXbUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXb4,    [Z14_FXbUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb5,    [Z14_FXbUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<LSU,     [Z14_LSUnit]>;
-  def : WriteRes<LSU2,    [Z14_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3,    [Z14_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU4,    [Z14_LSUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<LSU5,    [Z14_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<VecBF,   [Z14_VecUnit]>;
-  def : WriteRes<VecBF2,  [Z14_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecBF4,  [Z14_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDF,   [Z14_VecUnit]>;
-  def : WriteRes<VecDF2,  [Z14_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDF4,  [Z14_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDFX,  [Z14_VecUnit]>;
-  def : WriteRes<VecDFX2, [Z14_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDFX4, [Z14_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecFPd,  [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<FXa, [Z14_FXaUnit]>;
+  def : WriteRes<FXb, [Z14_FXbUnit]>;
+  def : WriteRes<LSU, [Z14_LSUnit]>;
+  def : WriteRes<VecBF,  [Z14_VecUnit]>;
+  def : WriteRes<VecDF,  [Z14_VecUnit]>;
+  def : WriteRes<VecDFX, [Z14_VecUnit]>;
   def : WriteRes<VecMul,  [Z14_VecUnit]>;
   def : WriteRes<VecStr,  [Z14_VecUnit]>;
   def : WriteRes<VecXsPm, [Z14_VecUnit]>;
-  def : WriteRes<VecXsPm2,[Z14_VecUnit]> { let ResourceCycles = [2]; }
-  // Virtual Branching Unit
-  def : WriteRes<VBU,     [Z14_VBUnit]>;
+  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
+  }}
+
+  def : WriteRes<VecFPd,  [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
+
+  def : WriteRes<VBU,     [Z14_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z14_MCD]> { let NumMicroOps = 3;

diff --git a/lib/Target/SystemZ/SystemZScheduleZ196.td b/lib/Target/SystemZ/SystemZScheduleZ196.td
index c328de843a7c7d8decf45d43b0bf6c75445255f5..3012b565d5ef03eb647304967b95e371084bd9bd 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -59,22 +59,9 @@ def : ReadAdvance<RegReadAdv, 4>;
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in {
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+  }
 }
 
 // Execution units.
@@ -86,22 +73,16 @@ def Z196_MCD    : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXU,       [Z196_FXUnit]>;
-  def : WriteRes<FXU2,      [Z196_FXUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXU3,      [Z196_FXUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXU4,      [Z196_FXUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXU5,      [Z196_FXUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FXU6,      [Z196_FXUnit]> { let ResourceCycles = [6]; }
-  def : WriteRes<LSU,       [Z196_LSUnit]>;
-  def : WriteRes<LSU2,      [Z196_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3,      [Z196_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU5,      [Z196_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FPU,       [Z196_FPUnit]>;
-  def : WriteRes<FPU2,      [Z196_FPUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FPU4,      [Z196_FPUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<DFU,       [Z196_DFUnit]>;
-  def : WriteRes<DFU2,      [Z196_DFUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<DFU4,      [Z196_DFUnit]> { let ResourceCycles = [4]; }
+  def : WriteRes<FXU, [Z196_FXUnit]>;
+  def : WriteRes<LSU, [Z196_LSUnit]>;
+  def : WriteRes<FPU, [Z196_FPUnit]>;
+  def : WriteRes<DFU, [Z196_DFUnit]>;
+  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
+    def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
+  }}
 }
 
 def : WriteRes<MCD, [Z196_MCD]> { let NumMicroOps = 3;

diff --git a/lib/Target/SystemZ/SystemZScheduleZEC12.td b/lib/Target/SystemZ/SystemZScheduleZEC12.td
index 0b3427be0a6ef099ca6ff4af343513188936f60d..892f493570d1ad5ffb59a6ca3f21176a99217e8a 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -59,22 +59,9 @@ def : ReadAdvance<RegReadAdv, 4>;
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in {
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+  }
 }
 
 // Execution units.
@@ -87,23 +74,17 @@ def ZEC12_MCD    : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXU,  [ZEC12_FXUnit]>;
-  def : WriteRes<FXU2, [ZEC12_FXUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXU3, [ZEC12_FXUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXU4, [ZEC12_FXUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXU5, [ZEC12_FXUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FXU6, [ZEC12_FXUnit]> { let ResourceCycles = [6]; }
-  def : WriteRes<LSU,  [ZEC12_LSUnit]>;
-  def : WriteRes<LSU2, [ZEC12_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3, [ZEC12_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU4, [ZEC12_LSUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<LSU5, [ZEC12_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FPU,  [ZEC12_FPUnit]>;
-  def : WriteRes<FPU2, [ZEC12_FPUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FPU4, [ZEC12_FPUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<DFU,  [ZEC12_DFUnit]>;
-  def : WriteRes<DFU2, [ZEC12_DFUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<DFU4, [ZEC12_DFUnit]> { let ResourceCycles = [4]; }
+  def : WriteRes<FXU, [ZEC12_FXUnit]>;
+  def : WriteRes<LSU, [ZEC12_LSUnit]>;
+  def : WriteRes<FPU, [ZEC12_FPUnit]>;
+  def : WriteRes<DFU, [ZEC12_DFUnit]>;
+  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
+    def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
+  }}
+
   def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
 }