[AArch64] Generate literals by the little end

ARM seems to prefer that long literals be formed from their little end in
order to promote the fusion of the instrs pairs MOV/MOVK and MOVK/MOVK on
Cortex A57 and others (v.  "Cortex A57 Software Optimisation Guide", section
4.14).

Differential revision: https://reviews.llvm.org/D28697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292422 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 6bfbce401e8367852d4e75e8cb2c0417a9aafb06..5b8a1e05d140c96570b456bbb3005803b456906c 100644 (file)
--- a/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -539,15 +539,15 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
   if (Imm != 0) {
     unsigned LZ = countLeadingZeros(Imm);
     unsigned TZ = countTrailingZeros(Imm);
-    Shift = ((63 - LZ) / 16) * 16;
-    LastShift = (TZ / 16) * 16;
+    Shift = (TZ / 16) * 16;
+    LastShift = ((63 - LZ) / 16) * 16;
   }
   unsigned Imm16 = (Imm >> Shift) & Mask;
   bool DstIsDead = MI.getOperand(0).isDead();
   MachineInstrBuilder MIB1 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
           .addReg(DstReg, RegState::Define |
-                              getDeadRegState(DstIsDead && Shift == LastShift))
+                  getDeadRegState(DstIsDead && Shift == LastShift))
           .addImm(Imm16)
           .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
 
@@ -564,15 +564,15 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
 
   MachineInstrBuilder MIB2;
   unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
-  while (Shift != LastShift) {
-    Shift -= 16;
+  while (Shift < LastShift) {
+    Shift += 16;
     Imm16 = (Imm >> Shift) & Mask;
     if (Imm16 == (isNeg ? Mask : 0))
       continue; // This 16-bit portion is already set correctly.
     MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
                .addReg(DstReg,
                        RegState::Define |
-                           getDeadRegState(DstIsDead && Shift == LastShift))
+                       getDeadRegState(DstIsDead && Shift == LastShift))
                .addReg(DstReg)
                .addImm(Imm16)
                .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));

diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index f5a2ee03c572d1de609e7e05bcd26e5a12e605b9..59c21eb84bb4a874b55850247d843afa285710cc 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1299,16 +1299,16 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
         .addMemOperand(*MI.memoperands_begin());
   } else if (TM.getCodeModel() == CodeModel::Large) {
     BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
     BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
         .addReg(Reg, RegState::Kill)
         .addImm(0)

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index 709de5b13e2cfe7eea4c8455fe504c854bb93cfd..96251cf12401a9aa0b0c1327df722cd2e2701784 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -576,31 +576,31 @@ def : Pat<(f64 fpimm:$in),
 // sequences.
 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
                              tglobaladdr:$g1, tglobaladdr:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
-                                  tglobaladdr:$g2, 32),
-                          tglobaladdr:$g1, 16),
-                  tglobaladdr:$g0, 0)>;
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),
+                                  tglobaladdr:$g1, 16),
+                          tglobaladdr:$g2, 32),
+                  tglobaladdr:$g3, 48)>;
 
 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
                              tblockaddress:$g1, tblockaddress:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
-                                  tblockaddress:$g2, 32),
-                          tblockaddress:$g1, 16),
-                  tblockaddress:$g0, 0)>;
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0),
+                                  tblockaddress:$g1, 16),
+                          tblockaddress:$g2, 32),
+                  tblockaddress:$g3, 48)>;
 
 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
                              tconstpool:$g1, tconstpool:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
-                                  tconstpool:$g2, 32),
-                          tconstpool:$g1, 16),
-                  tconstpool:$g0, 0)>;
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0),
+                                  tconstpool:$g1, 16),
+                          tconstpool:$g2, 32),
+                  tconstpool:$g3, 48)>;
 
 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
                              tjumptable:$g1, tjumptable:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
-                                  tjumptable:$g2, 32),
-                          tjumptable:$g1, 16),
-                  tjumptable:$g0, 0)>;
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0),
+                                  tjumptable:$g1, 16),
+                          tjumptable:$g2, 32),
+                  tjumptable:$g3, 48)>;
 
 
 //===----------------------------------------------------------------------===//

diff --git a/test/CodeGen/AArch64/arm64-addrmode.ll b/test/CodeGen/AArch64/arm64-addrmode.ll
index e8fc4e68fcbe2372842ec92640d4d02b35c909da..6da767921632fec66919acdec7794984f4dd9b2e 100644 (file)
--- a/test/CodeGen/AArch64/arm64-addrmode.ll
+++ b/test/CodeGen/AArch64/arm64-addrmode.ll
@@ -112,8 +112,8 @@ define void @t10(i64 %a) {
 
 define void @t11(i64 %a) {
 ; CHECK-LABEL: t11:
-; CHECK: mov w[[NUM:[0-9]+]], #19070976
-; CHECK: movk w[[NUM:[0-9]+]], #17767
+; CHECK: mov w[[NUM:[0-9]+]], #17767
+; CHECK: movk w[[NUM:[0-9]+]], #291
 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
   %1 = add i64 %a, 19088743   ;0x1234567
   %2 = inttoptr i64 %1 to i64*

diff --git a/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/test/CodeGen/AArch64/arm64-bitfield-extract.ll
index 339dbbe18fc09ffb8c2086f3503ede32955272cb..91aed060677aeb1a2d715a2578e6c29393c6b0bb 100644 (file)
--- a/test/CodeGen/AArch64/arm64-bitfield-extract.ll
+++ b/test/CodeGen/AArch64/arm64-bitfield-extract.ll
@@ -348,8 +348,8 @@ entry:
 ; CHECK-LABEL: fct16:
 ; CHECK: ldr [[REG1:w[0-9]+]],
 ; Create the constant
-; CHECK: mov [[REGCST:w[0-9]+]], #1703936
-; CHECK: movk [[REGCST]], #33120
+; CHECK: mov [[REGCST:w[0-9]+]], #33120
+; CHECK: movk [[REGCST]], #26, lsl #16
 ; Do the masking
 ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
 ; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3
@@ -377,8 +377,8 @@ entry:
 ; CHECK-LABEL: fct17:
 ; CHECK: ldr [[REG1:x[0-9]+]],
 ; Create the constant
-; CHECK: mov w[[REGCST:[0-9]+]], #1703936
-; CHECK: movk w[[REGCST]], #33120
+; CHECK: mov w[[REGCST:[0-9]+]], #33120
+; CHECK: movk w[[REGCST]], #26, lsl #16
 ; Do the masking
 ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
 ; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3

diff --git a/test/CodeGen/AArch64/arm64-blockaddress.ll b/test/CodeGen/AArch64/arm64-blockaddress.ll
index 5df8402163520c4e45f1ed7670ee5629f2f74817..b50ffdef5ddd50c9df94c76097310bdbed98771d 100644 (file)
--- a/test/CodeGen/AArch64/arm64-blockaddress.ll
+++ b/test/CodeGen/AArch64/arm64-blockaddress.ll
@@ -15,10 +15,10 @@ entry:
 ; CHECK-LINUX: add {{x[0-9]+}}, [[REG]], :lo12:.Ltmp1
 
 ; CHECK-LARGE-LABEL: t:
-; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
 
   %recover = alloca i64, align 8
   store volatile i64 ptrtoint (i8* blockaddress(@t, %mylabel) to i64), i64* %recover, align 8

diff --git a/test/CodeGen/AArch64/arm64-code-model-large-abs.ll b/test/CodeGen/AArch64/arm64-code-model-large-abs.ll
index 9f50fea370e402eaabb0c63db4e97e030bfd55be..171941748c8fd8aff593730ffdca998468e98359 100644 (file)
--- a/test/CodeGen/AArch64/arm64-code-model-large-abs.ll
+++ b/test/CodeGen/AArch64/arm64-code-model-large-abs.ll
@@ -9,10 +9,10 @@ define i8* @global_addr() {
 ; CHECK-LABEL: global_addr:
   ret i8* @var8
   ; The movz/movk calculation should end up returned directly in x0.
-; CHECK: movz x0, #:abs_g3:var8
-; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movz x0, #:abs_g0_nc:var8
 ; CHECK: movk x0, #:abs_g1_nc:var8
-; CHECK: movk x0, #:abs_g0_nc:var8
+; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movk x0, #:abs_g3:var8
 ; CHECK-NEXT: ret
 }
 
@@ -20,10 +20,10 @@ define i8 @global_i8() {
 ; CHECK-LABEL: global_i8:
   %val = load i8, i8* @var8
   ret i8 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
 ; CHECK: ldrb w0, [x[[ADDR_REG]]]
 }
 
@@ -31,10 +31,10 @@ define i16 @global_i16() {
 ; CHECK-LABEL: global_i16:
   %val = load i16, i16* @var16
   ret i16 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
 ; CHECK: ldrh w0, [x[[ADDR_REG]]]
 }
 
@@ -42,10 +42,10 @@ define i32 @global_i32() {
 ; CHECK-LABEL: global_i32:
   %val = load i32, i32* @var32
   ret i32 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
 ; CHECK: ldr w0, [x[[ADDR_REG]]]
 }
 
@@ -53,10 +53,10 @@ define i64 @global_i64() {
 ; CHECK-LABEL: global_i64:
   %val = load i64, i64* @var64
   ret i64 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
 ; CHECK: ldr x0, [x[[ADDR_REG]]]
 }
 
@@ -64,9 +64,9 @@ define <2 x i64> @constpool() {
 ; CHECK-LABEL: constpool:
   ret <2 x i64> <i64 123456789, i64 987654321100>
 
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:[[CPADDR]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:[[CPADDR]]
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:[[CPADDR]]
 ; CHECK: ldr q0, [x[[ADDR_REG]]]
 }

diff --git a/test/CodeGen/AArch64/arm64-const-addr.ll b/test/CodeGen/AArch64/arm64-const-addr.ll
index e55db29044894215fecbeca217d3af23828f118d..bbb1ce4aced72c9f5ca1c2eeea8fa2d94d6fd758 100644 (file)
--- a/test/CodeGen/AArch64/arm64-const-addr.ll
+++ b/test/CodeGen/AArch64/arm64-const-addr.ll
@@ -5,8 +5,8 @@
 ; Test if the constant base address gets only materialized once.
 define i32 @test1() nounwind {
 ; CHECK-LABEL:  test1
-; CHECK:        mov  w8, #68091904
-; CHECK-NEXT:   movk  w8, #49152
+; CHECK:        mov  w8, #49152
+; CHECK-NEXT:   movk  w8, #1039, lsl #16
 ; CHECK-NEXT:   ldp w9, w10, [x8, #4]
 ; CHECK:        ldr w8, [x8, #12]
   %at = inttoptr i64 68141056 to %T*

diff --git a/test/CodeGen/AArch64/arm64-extern-weak.ll b/test/CodeGen/AArch64/arm64-extern-weak.ll
index f00efbcea7804233b912faadd33ca2255522696e..990782cb69a00d861341a66a3e03b2ef79c8a3e4 100644 (file)
--- a/test/CodeGen/AArch64/arm64-extern-weak.ll
+++ b/test/CodeGen/AArch64/arm64-extern-weak.ll
@@ -15,10 +15,10 @@ define i32()* @foo() {
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz x0, #:abs_g3:var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movk x0, #:abs_g3:var
 }
 
 
@@ -33,10 +33,10 @@ define i32* @bar() {
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g0_nc:arr_var
 ; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g1_nc:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g0_nc:arr_var
+; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g3:arr_var
 }
 
 @defined_weak_var = internal unnamed_addr global i32 0
@@ -46,8 +46,8 @@ define i32* @wibble() {
 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
 
-; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
 }

diff --git a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
index 9dae7a6f5b6902269a47e9677b383a3000d7f06c..4aa10da7243d92224ca72d9a671a29ca41d3d289 100644 (file)
--- a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
@@ -37,9 +37,9 @@ entry:
 define signext i8 @foo3() nounwind ssp {
 entry:
 ; CHECK-LABEL: @foo3
-; CHECK: mov x[[REG:[0-9]+]], #12343736008704
+; CHECK: mov x[[REG:[0-9]+]], #12274
 ; CHECK: movk x[[REG]], #29646, lsl #16
-; CHECK: movk x[[REG]], #12274
+; CHECK: movk x[[REG]], #2874, lsl #32
   %0 = load i8*, i8** @pd2, align 8
   %arrayidx = getelementptr inbounds i8, i8* %0, i64 12345678901234
   %1 = load i8, i8* %arrayidx, align 1

diff --git a/test/CodeGen/AArch64/arm64-movi.ll b/test/CodeGen/AArch64/arm64-movi.ll
index c24490665d62c68652193b290acbcb286c2ab81b..8d6caa81d97854a29eab67406d59be154be9f29e 100644 (file)
--- a/test/CodeGen/AArch64/arm64-movi.ll
+++ b/test/CodeGen/AArch64/arm64-movi.ll
@@ -51,24 +51,24 @@ define i32 @movz() nounwind {
 
 define i64 @movz_3movk() nounwind {
 ; CHECK-LABEL: movz_3movk:
-; CHECK:      mov x0, #1407374883553280
-; CHECK-NEXT: movk x0, #4660, lsl #32
+; CHECK:      mov x0, #22136
 ; CHECK-NEXT: movk x0, #43981, lsl #16
-; CHECK-NEXT: movk x0, #22136
+; CHECK-NEXT: movk x0, #4660, lsl #32
+; CHECK-NEXT: movk x0, #5, lsl #48
   ret i64 1427392313513592
 }
 
 define i64 @movz_movk_skip1() nounwind {
 ; CHECK-LABEL: movz_movk_skip1:
-; CHECK:      mov x0, #21474836480
-; CHECK-NEXT: movk x0, #17185, lsl #16
+; CHECK:      mov x0, #1126236160
+; CHECK-NEXT: movk x0, #5, lsl #32
   ret i64 22601072640
 }
 
 define i64 @movz_skip1_movk() nounwind {
 ; CHECK-LABEL: movz_skip1_movk:
-; CHECK:      mov x0, #147695335374848
-; CHECK-NEXT: movk x0, #4660
+; CHECK:      mov x0, #4660
+; CHECK-NEXT: movk x0, #34388, lsl #32
   ret i64 147695335379508
 }
 
@@ -84,8 +84,8 @@ define i64 @movn() nounwind {
 
 define i64 @movn_skip1_movk() nounwind {
 ; CHECK-LABEL: movn_skip1_movk:
-; CHECK:      mov x0, #-176093659137
-; CHECK-NEXT: movk x0, #4660
+; CHECK:      mov x0, #-60876
+; CHECK-NEXT: movk x0, #65494, lsl #32
   ret i64 -176093720012
 }
 
@@ -195,8 +195,8 @@ define i64 @orr_movk13() nounwind {
 ; rdar://13944082
 define i64 @g() nounwind {
 ; CHECK-LABEL: g:
-; CHECK: mov x0, #-281474976710656
-; CHECK: movk x0, #2
+; CHECK: mov x0, #2
+; CHECK: movk x0, #65535, lsl #48
 entry:
   ret i64 -281474976710654
 }

diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll
index 735be244d4575da73de16f99232df90f6d391edf..42b0051a2dd6007261a86290671233a000a73649 100644 (file)
--- a/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/test/CodeGen/AArch64/bitfield-insert.ll
@@ -428,8 +428,8 @@ define i32 @test5(i32 %a) {
 ; BFXIL will use the same constant as the ORR, so we don't care how the constant
 ; is materialized (it's an equal cost either way).
 ; CHECK-LABEL: @test6
-; CHECK: mov [[REG:w[0-9]+]], #720896
-; CHECK: movk [[REG]], #23250
+; CHECK: mov [[REG:w[0-9]+]], #23250
+; CHECK: movk [[REG]], #11, lsl #16
 ; CHECK: bfxil w0, [[REG]], #0, #20
 define i32 @test6(i32 %a) {
   %1 = and i32 %a, 4293918720 ; 0xfff00000
@@ -440,8 +440,8 @@ define i32 @test6(i32 %a) {
 ; BFIs that require the same number of instruction to materialize the constant
 ; as the original ORR are okay.
 ; CHECK-LABEL: @test7
-; CHECK: mov [[REG:w[0-9]+]], #327680
-; CHECK: movk [[REG]], #44393
+; CHECK: mov [[REG:w[0-9]+]], #44393
+; CHECK: movk [[REG]], #5, lsl #16
 ; CHECK: bfi w0, [[REG]], #1, #19
 define i32 @test7(i32 %a) {
   %1 = and i32 %a, 4293918721 ; 0xfff00001
@@ -454,9 +454,9 @@ define i32 @test7(i32 %a) {
 ; 'and' with a 'movk', which would decrease ILP while using the same number of
 ; instructions.
 ; CHECK-LABEL: @test8
-; CHECK: mov [[REG2:x[0-9]+]], #157599529959424
+; CHECK: mov [[REG2:x[0-9]+]], #2035482624
 ; CHECK: and [[REG1:x[0-9]+]], x0, #0xff000000000000ff
-; CHECK: movk [[REG2]], #31059, lsl #16
+; CHECK: movk [[REG2]], #36694, lsl #32
 ; CHECK: orr x0, [[REG1]], [[REG2]]
 define i64 @test8(i64 %a) {
   %1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff

diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll
index 7c0755a13d0e04ffbe76bf08407ae7d432975aad..3683332c2c64af5393a4214b86e7a5ef524ec8ca 100644 (file)
--- a/test/CodeGen/AArch64/blockaddress.ll
+++ b/test/CodeGen/AArch64/blockaddress.ll
@@ -14,10 +14,10 @@ define void @test_blockaddress() {
 ; CHECK: ldr [[NEWDEST:x[0-9]+]]
 ; CHECK: br [[NEWDEST]]
 
-; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
 ; CHECK-LARGE: str [[ADDR_REG]],
 ; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]]
 ; CHECK-LARGE: br [[NEWDEST]]

diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll
index 1680815d93ea4fe4a23d6614f6ab98750da96d27..82169acc3e5614807d10064e4ff353dd4553bcc2 100644 (file)
--- a/test/CodeGen/AArch64/code-model-large-abs.ll
+++ b/test/CodeGen/AArch64/code-model-large-abs.ll
@@ -9,10 +9,10 @@ define i8* @global_addr() {
 ; CHECK-LABEL: global_addr:
   ret i8* @var8
   ; The movz/movk calculation should end up returned directly in x0.
-; CHECK: movz x0, #:abs_g3:var8
-; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movz x0, #:abs_g0_nc:var8
 ; CHECK: movk x0, #:abs_g1_nc:var8
-; CHECK: movk x0, #:abs_g0_nc:var8
+; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movk x0, #:abs_g3:var8
 ; CHECK-NEXT: ret
 }
 
@@ -20,10 +20,10 @@ define i8 @global_i8() {
 ; CHECK-LABEL: global_i8:
   %val = load i8, i8* @var8
   ret i8 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
 ; CHECK: ldrb w0, [x[[ADDR_REG]]]
 }
 
@@ -31,10 +31,10 @@ define i16 @global_i16() {
 ; CHECK-LABEL: global_i16:
   %val = load i16, i16* @var16
   ret i16 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
 ; CHECK: ldrh w0, [x[[ADDR_REG]]]
 }
 
@@ -42,10 +42,10 @@ define i32 @global_i32() {
 ; CHECK-LABEL: global_i32:
   %val = load i32, i32* @var32
   ret i32 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
 ; CHECK: ldr w0, [x[[ADDR_REG]]]
 }
 
@@ -53,9 +53,9 @@ define i64 @global_i64() {
 ; CHECK-LABEL: global_i64:
   %val = load i64, i64* @var64
   ret i64 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
 ; CHECK: ldr x0, [x[[ADDR_REG]]]
 }

diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll
index 921009cf821db28bc1044cde0de98e4e08eeea83..ac2153ad8ffed71db1e9d746df2bcd9af34783d7 100644 (file)
--- a/test/CodeGen/AArch64/extern-weak.ll
+++ b/test/CodeGen/AArch64/extern-weak.ll
@@ -16,10 +16,10 @@ define i32()* @foo() {
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz x0, #:abs_g3:var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movk x0, #:abs_g3:var
 }
 
 
@@ -37,10 +37,10 @@ define i32* @bar() {
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g3:arr_var
-; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g0_nc:arr_var
 ; CHECK-LARGE: movk [[ADDR]], #:abs_g1_nc:arr_var
-; CHECK-LARGE: movk [[ADDR]], #:abs_g0_nc:arr_var
+; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movk [[ADDR]], #:abs_g3:arr_var
 }
 
 @defined_weak_var = internal unnamed_addr global i32 0
@@ -51,8 +51,8 @@ define i32* @wibble() {
 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
 
-; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
 }

diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll
index b4faef750a2c36f9e13b30356cb9ebc440b15845..d19777c4d27e4bddc355dcbbc8c0b61b6f034257 100644 (file)
--- a/test/CodeGen/AArch64/fpimm.ll
+++ b/test/CodeGen/AArch64/fpimm.ll
@@ -38,18 +38,18 @@ define void @check_double() {
 }
 
 ; LARGE-LABEL: check_float2
-; LARGE:       mov [[REG:w[0-9]+]], #1078525952
-; LARGE-NEXT:  movk [[REG]], #4059
+; LARGE:       mov [[REG:w[0-9]+]], #4059
+; LARGE-NEXT:  movk [[REG]], #16457, lsl #16
 ; LARGE-NEXT:  fmov s0, [[REG]]
 define float @check_float2() {
   ret float 3.14159274101257324218750
 }
 
 ; LARGE-LABEL: check_double2
-; LARGE:       mov [[REG:x[0-9]+]], #4614219293217783808
-; LARGE-NEXT:  movk [[REG]], #8699, lsl #32
+; LARGE:       mov [[REG:x[0-9]+]], #11544
 ; LARGE-NEXT:  movk [[REG]], #21572, lsl #16
-; LARGE-NEXT:  movk [[REG]], #11544
+; LARGE-NEXT:  movk [[REG]], #8699, lsl #32
+; LARGE-NEXT:  movk [[REG]], #16393, lsl #48
 ; LARGE-NEXT:  fmov d0, [[REG]]
 define double @check_double2() {
   ret double 3.1415926535897931159979634685441851615905761718750

diff --git a/test/CodeGen/AArch64/jump-table.ll b/test/CodeGen/AArch64/jump-table.ll
index d6a7fceac84da97ce6618c7a73bebc276a143fdb..f71d4356be35a8279651a4a9ec6f20034e00a9c9 100644 (file)
--- a/test/CodeGen/AArch64/jump-table.ll
+++ b/test/CodeGen/AArch64/jump-table.ll
@@ -16,10 +16,10 @@ define i32 @test_jumptable(i32 %in) {
 ; CHECK: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3]
 ; CHECK: br [[DEST]]
 
-; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g3:.LJTI0_0
-; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
+; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g0_nc:.LJTI0_0
 ; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0
-; CHECK-LARGE: movk x[[JTADDR]], #:abs_g0_nc:.LJTI0_0
+; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
+; CHECK-LARGE: movk x[[JTADDR]], #:abs_g3:.LJTI0_0
 ; CHECK-LARGE: ldr [[DEST:x[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}, lsl #3]
 ; CHECK-LARGE: br [[DEST]]
 

diff --git a/test/CodeGen/AArch64/large-consts.ll b/test/CodeGen/AArch64/large-consts.ll
index 6bf85e829f61e821e273cfce22b82d088ef7499c..e351c3530696175ca4a85045836eb8bd396f3d43 100644 (file)
--- a/test/CodeGen/AArch64/large-consts.ll
+++ b/test/CodeGen/AArch64/large-consts.ll
@@ -5,10 +5,10 @@
 
 define double @foo() {
 
-; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0   // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
-; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
+; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g0_nc:.LCPI0_0   // encoding: [0bAAA01000,A,0b100AAAAA,0xd2]
 ; CHECK: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b101AAAAA,0xf2]
-; CHECK: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b100AAAAA,0xf2]
+; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
+; CHECK: movk [[CPADDR]], #:abs_g3:.LCPI0_0 // encoding: [0bAAA01000,A,0b111AAAAA,0xf2]
 
   ret double 3.14159
 }

diff --git a/test/CodeGen/AArch64/literal_pools_float.ll b/test/CodeGen/AArch64/literal_pools_float.ll
index f5d6a17f3a11441d9414b988d58230be6e69fa96..6ad685ad7c4952e42a8f56404e1914279b65994f 100644 (file)
--- a/test/CodeGen/AArch64/literal_pools_float.ll
+++ b/test/CodeGen/AArch64/literal_pools_float.ll
@@ -15,10 +15,10 @@ define void @floating_lits() {
 ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
 
-; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
 ; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]]
 ; CHECK-LARGE: fadd
 ; CHECK-NOFP-LARGE-NOT: ldr {{s[0-9]+}},
@@ -33,10 +33,10 @@ define void @floating_lits() {
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
 ; CHECK-NOFP-NOT: fadd
 
-; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
 ; CHECK-LARGE: ldr {{d[0-9]+}}, [x[[LITADDR]]]
 ; CHECK-NOFP-LARGE-NOT: ldr {{d[0-9]+}},
 

diff --git a/test/CodeGen/AArch64/movw-shift-encoding.ll b/test/CodeGen/AArch64/movw-shift-encoding.ll
index 178fccce333b06043b76c259fbbdb4c88f08906d..673bd85bd1674297b53ad7dc5a45685412bef49f 100644 (file)
--- a/test/CodeGen/AArch64/movw-shift-encoding.ll
+++ b/test/CodeGen/AArch64/movw-shift-encoding.ll
@@ -8,8 +8,8 @@
 define i32* @get_var() {
   ret i32* @var
 
-; CHECK: movz    x0, #:abs_g3:var        // encoding: [0bAAA00000,A,0b111AAAAA,0xd2]
-; CHECK: movk    x0, #:abs_g2_nc:var     // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
-; CHECK: movk    x0, #:abs_g1_nc:var     // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
-; CHECK: movk    x0, #:abs_g0_nc:var     // encoding: [0bAAA00000,A,0b100AAAAA,0xf2]
+; CHECK: movz    x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xd2]
+; CHECK: movk    x0, #:abs_g1_nc:var // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
+; CHECK: movk    x0, #:abs_g2_nc:var // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
+; CHECK: movk    x0, #:abs_g3:var    // encoding: [0bAAA00000,A,0b111AAAAA,0xf2]
 }

diff --git a/test/CodeGen/AArch64/stack_guard_remat.ll b/test/CodeGen/AArch64/stack_guard_remat.ll
index d6bae62e5edcff26cea140907efd73fc500cd201..08c8a4b665720df2cc8c2178ca66603c53f21d6a 100644 (file)
--- a/test/CodeGen/AArch64/stack_guard_remat.ll
+++ b/test/CodeGen/AArch64/stack_guard_remat.ll
@@ -15,10 +15,10 @@
 ; PIC-LINUX: ldr {{x[0-9]+}}, {{\[}}[[R1]]{{\]}}
 
 ; STATIC-LARGE: foo2
-; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g3:__stack_chk_guard
-; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
+; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g0_nc:__stack_chk_guard
 ; STATIC-LARGE: movk [[R0]], #:abs_g1_nc:__stack_chk_guard
-; STATIC-LARGE: movk [[R0]], #:abs_g0_nc:__stack_chk_guard
+; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
+; STATIC-LARGE: movk [[R0]], #:abs_g3:__stack_chk_guard
 ; STATIC-LARGE: ldr {{x[0-9]+}}, {{\[}}[[R0]]{{\]}}
 
 ; STATIC-SMALL: foo2