RA: Remove another assert on empty intervals

This case is similar to the one fixed in r308808,
except when rematerializing.

Fixes bug 33884.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308813 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp
index 4e6a3ec218666b2bddb7dfaf4d9f049bfd44bbf7..407fd2477a67d632649e4db2ed85d3c6ed91575e 100644 (file)
--- a/lib/CodeGen/InlineSpiller.cpp
+++ b/lib/CodeGen/InlineSpiller.cpp
@@ -643,8 +643,8 @@ void InlineSpiller::reMaterializeAll() {
       Edit->eraseVirtReg(Reg);
       continue;
     }
-    assert((LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty()) &&
-           "Reg with empty interval has reference");
+
+    assert(LIS.hasInterval(Reg) && "Reg with no interval");
     RegsToSpill[ResultPos++] = Reg;
   }
   RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());

diff --git a/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
index 68bd8c45dcb04d78a473b1c3196da8cbca1d017f..bb58da7a59f63a10e5133bc72dd6e82c988b0d3d 100644 (file)
--- a/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
+++ b/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
@@ -38,3 +38,37 @@ body:             |
     S_ENDPGM
 
 ...
+
+# Similar assert which happens when trying to rematerialize.
+# https://bugs.llvm.org/show_bug.cgi?id=33884
+---
+# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
+
+# CHECK-NOT: MOV
+# CHECK: undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+
+# CHECK: bb.1:
+# CHECK-NEXT: S_NOP 0, implicit %3.sub2
+# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
+# CHECK-NEXT: undef %4.sub2 = V_MOV_B32_e32 0, implicit %exec
+# CHECK-NEXT: S_NOP 0, implicit %4.sub2
+name: rematerialize_empty_interval_has_reference
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vreg_128, preferred-register: '' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '' }
+  - { id: 3, class: vreg_128, preferred-register: '' }
+body:             |
+  bb.0:
+    successors: %bb.1
+
+    undef %0.sub2 = V_MOV_B32_e32 0, implicit %exec
+    undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+
+  bb.1:
+    S_NOP 0, implicit %3.sub2
+    S_NOP 0, implicit undef %0.sub0
+    S_NOP 0, implicit %0.sub2
+
+...