#define SARADC_XPD_HALL_FORCE_V 0x1\r
#define SARADC_XPD_HALL_FORCE_S 26\r
/* SARADC_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
-/*description: 1: wakeup interrupt is generated if SET1 is ��touched�� 0:\r
- wakeup interrupt is generated only if SET1 & SET2 is both ��touched��*/\r
+/*description: 1: wakeup interrupt is generated if SET1 is "touched" 0:\r
+ wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/\r
#define SARADC_TOUCH_OUT_1EN (BIT(25))\r
#define SARADC_TOUCH_OUT_1EN_M (BIT(25))\r
#define SARADC_TOUCH_OUT_1EN_V 0x1\r
#define SARADC_TOUCH_OUT_1EN_S 25\r
/* SARADC_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
/*description: 1: when the counter is greater then the threshold the touch\r
- pad is considered as ��touched�� 0: when the counter is less than the threshold the touch pad is considered as ��touched��*/\r
+ pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched"*/\r
#define SARADC_TOUCH_OUT_SEL (BIT(24))\r
#define SARADC_TOUCH_OUT_SEL_M (BIT(24))\r
#define SARADC_TOUCH_OUT_SEL_V 0x1\r
#define SARADC_TOUCH_MEAS_DONE_V 0x1\r
#define SARADC_TOUCH_MEAS_DONE_S 10\r
/* SARADC_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: 10-bit register to indicate which pads are ��touched��*/\r
+/*description: 10-bit register to indicate which pads are "touched"*/\r
#define SARADC_TOUCH_MEAS_EN 0x000003FF\r
#define SARADC_TOUCH_MEAS_EN_M ((SARADC_TOUCH_MEAS_EN_V)<<(SARADC_TOUCH_MEAS_EN_S))\r
#define SARADC_TOUCH_MEAS_EN_V 0x3FF\r
#define SARADC_SAR_TOUCH_ENABLE_REG (DR_REG_SARADC_BASE + 0x008c)\r
/* SARADC_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */\r
/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is\r
- ��touched�� only if at least one of touch pad in SET1 is ��touched��.*/\r
+ "touched" only if at least one of touch pad in SET1 is "touched".*/\r
#define SARADC_TOUCH_PAD_OUTEN1 0x000003FF\r
#define SARADC_TOUCH_PAD_OUTEN1_M ((SARADC_TOUCH_PAD_OUTEN1_V)<<(SARADC_TOUCH_PAD_OUTEN1_S))\r
#define SARADC_TOUCH_PAD_OUTEN1_V 0x3FF\r
#define SARADC_TOUCH_PAD_OUTEN1_S 20\r
/* SARADC_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */\r
/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is\r
- ��touched�� only if at least one of touch pad in SET2 is ��touched��.*/\r
+ "touched" only if at least one of touch pad in SET2 is "touched".*/\r
#define SARADC_TOUCH_PAD_OUTEN2 0x000003FF\r
#define SARADC_TOUCH_PAD_OUTEN2_M ((SARADC_TOUCH_PAD_OUTEN2_V)<<(SARADC_TOUCH_PAD_OUTEN2_S))\r
#define SARADC_TOUCH_PAD_OUTEN2_V 0x3FF\r
#define SPI_FREAD_QUAD_V 0x1\r
#define SPI_FREAD_QUAD_S 20\r
/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */\r
-/*description: The Device ID is read out to SPI_RD_STATUS register£¬ this bit\r
+/*description: The Device ID is read out to SPI_RD_STATUS register, this bit\r
combine with spi_flash_res bit. 1: enable 0: disable.*/\r
#define SPI_RESANDRES (BIT(15))\r
#define SPI_RESANDRES_M (BIT(15))\r
\r
#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)\r
/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */\r
-/*description: In the slave mode£¬it is the status for master to read out.*/\r
+/*description: In the slave mode,it is the status for master to read out.*/\r
#define SPI_STATUS_EXT 0x000000FF\r
#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S))\r
#define SPI_STATUS_EXT_V 0xFF\r
#define SPI_STATUS_EXT_S 24\r
/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */\r
-/*description: Mode bits in the flash fast read mode£¬ it is combined with spi_fastrd_mode bit.*/\r
+/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/\r
#define SPI_WB_MODE 0x000000FF\r
#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S))\r
#define SPI_WB_MODE_V 0xFF\r
#define SPI_WB_MODE_S 16\r
/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
-/*description: In the slave mode£¬ it is the status for master to read out.*/\r
+/*description: In the slave mode, it is the status for master to read out.*/\r
#define SPI_STATUS 0x0000FFFF\r
#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S))\r
#define SPI_STATUS_V 0xFFFF\r
#define SPI_MISO_DELAY_MODE_V 0x3\r
#define SPI_MISO_DELAY_MODE_S 16\r
/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */\r
-/*description: modify spi clock duty ratio when the value is lager than 8£¬\r
+/*description: modify spi clock duty ratio when the value is lager than 8,\r
the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/\r
#define SPI_CK_OUT_HIGH_MODE 0x0000000F\r
#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))\r
#define SPI_CK_OUT_HIGH_MODE_V 0xF\r
#define SPI_CK_OUT_HIGH_MODE_S 12\r
/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */\r
-/*description: modify spi clock duty ratio when the value is lager than 8£¬\r
+/*description: modify spi clock duty ratio when the value is lager than 8,\r
the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/\r
#define SPI_CK_OUT_LOW_MODE 0x0000000F\r
#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S))\r
#define SPI_CK_OUT_LOW_MODE_V 0xF\r
#define SPI_CK_OUT_LOW_MODE_S 8\r
/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */\r
-/*description: delay cycles of cs pin by spi clock£¬ this bits combined with spi_cs_hold bit.*/\r
+/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/\r
#define SPI_HOLD_TIME 0x0000000F\r
#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S))\r
#define SPI_HOLD_TIME_V 0xF\r
#define SPI_HOLD_TIME_S 4\r
/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */\r
-/*description: (cycles-1) of ¡°prepare¡± phase by spi clock£¬ this bits combined\r
+/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined\r
with spi_cs_setup bit.*/\r
#define SPI_SETUP_TIME 0x0000000F\r
#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))\r
#define SPI_CK_DIS_V 0x1\r
#define SPI_CK_DIS_S 5\r
/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */\r
-/*description: SPI CS2 pin enable£¬ 1: disable CS2£¬ 0: spi_cs2 signal is from/to CS2 pin*/\r
+/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/\r
#define SPI_CS2_DIS (BIT(2))\r
#define SPI_CS2_DIS_M (BIT(2))\r
#define SPI_CS2_DIS_V 0x1\r
#define SPI_CS2_DIS_S 2\r
/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */\r
-/*description: SPI CS1 pin enable£¬ 1: disable CS1£¬ 0: spi_cs1 signal is from/to CS1 pin*/\r
+/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/\r
#define SPI_CS1_DIS (BIT(1))\r
#define SPI_CS1_DIS_M (BIT(1))\r
#define SPI_CS1_DIS_V 0x1\r
#define SPI_CS1_DIS_S 1\r
/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: SPI CS0 pin enable£¬ 1: disable CS0£¬ 0: spi_cs0 signal is from/to CS0 pin*/\r
+/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/\r
#define SPI_CS0_DIS (BIT(0))\r
#define SPI_CS0_DIS_M (BIT(0))\r
#define SPI_CS0_DIS_V 0x1\r
\r
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38)\r
/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: Software reset enable£¬ reset the spi clock line cs line and data lines.*/\r
+/*description: Software reset enable, reset the spi clock line cs line and data lines.*/\r
#define SPI_SYNC_RESET (BIT(31))\r
#define SPI_SYNC_RESET_M (BIT(31))\r
#define SPI_SYNC_RESET_V 0x1\r
#define UART_SW_XOFF_INT_RAW_V 0x1\r
#define UART_SW_XOFF_INT_RAW_S 10\r
/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver recevies\r
+/*description: This interrupt raw bit turns to high level when receiver receives\r
xoff char with uart_sw_flow_con_en is set to 1.*/\r
#define UART_SW_XON_INT_RAW (BIT(9))\r
#define UART_SW_XON_INT_RAW_M (BIT(9))\r
\r
#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)\r
/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */\r
-/*description: This register is used to select the clock.1��apb clock��ref_tick*/\r
+/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/\r
#define UART_TICK_REF_ALWAYS_ON (BIT(27))\r
#define UART_TICK_REF_ALWAYS_ON_M (BIT(27))\r
#define UART_TICK_REF_ALWAYS_ON_V 0x1\r
#define UART_TICK_REF_ALWAYS_ON_S 27\r
/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: 1��receiver stops storing data int fifo when data is wrong.\r
- 0��receiver stores the data even if the received data is wrong.*/\r
+/*description: 1.receiver stops storing data int fifo when data is wrong.\r
+ 0.receiver stores the data even if the received data is wrong.*/\r
#define UART_ERR_WR_MASK (BIT(26))\r
#define UART_ERR_WR_MASK_M (BIT(26))\r
#define UART_ERR_WR_MASK_V 0x1\r
#define UART_ERR_WR_MASK_S 26\r
/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */\r
-/*description: 1��force clock on for registers��support clock only when write registers*/\r
+/*description: 1.force clock on for registers.support clock only when write registers*/\r
#define UART_CLK_EN (BIT(25))\r
#define UART_CLK_EN_M (BIT(25))\r
#define UART_CLK_EN_V 0x1\r
#define UART_IRDA_TX_INV_V 0x1\r
#define UART_IRDA_TX_INV_S 12\r
/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: 1��the irda transmitter's 11th bit is the same to the 10th bit.\r
- 0��set irda transmitter's 11th bit to 0.*/\r
+/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit.\r
+ 0.set irda transmitter's 11th bit to 0.*/\r
#define UART_IRDA_WCTL (BIT(11))\r
#define UART_IRDA_WCTL_M (BIT(11))\r
#define UART_IRDA_WCTL_V 0x1\r
#define UART_RX_FLOW_EN_V 0x1\r
#define UART_RX_FLOW_EN_S 23\r
/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */\r
-/*description: when receiver receives more data than its threshold value��\r
+/*description: when receiver receives more data than its threshold value.\r
receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/\r
#define UART_RX_FLOW_THRHD 0x0000007F\r
#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))\r
#define UART_RX_FLOW_THRHD_S 16\r
/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */\r
/*description: when the data amount in transmitter fifo is less than its threshold\r
- value�� it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/\r
+ value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/\r
#define UART_TXFIFO_EMPTY_THRHD 0x0000007F\r
#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))\r
#define UART_TXFIFO_EMPTY_THRHD_V 0x7F\r
#define UART_TXFIFO_EMPTY_THRHD_S 8\r
/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */\r
-/*description: When receiver receives more data than its threshold value��receiver\r
+/*description: When receiver receives more data than its threshold value.receiver\r
will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/\r
#define UART_RXFIFO_FULL_THRHD 0x0000007F\r
#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))\r
#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)\r
/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
/*description: This register stores the value of the minimum duration time for\r
- the low level pulse�� it is used in baudrate-detect process.*/\r
+ the low level pulse. it is used in baudrate-detect process.*/\r
#define UART_LOWPULSE_MIN_CNT 0x000FFFFF\r
#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))\r
#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF\r
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)\r
/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
/*description: This register stores the value of the maxinum duration time\r
- for the high level pulse�� it is used in baudrate-detect process.*/\r
+ for the high level pulse. it is used in baudrate-detect process.*/\r
#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF\r
#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))\r
#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF\r
\r
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)\r
/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register stores the count of rxd edge change�� it is used\r
+/*description: This register stores the count of rxd edge change. it is used\r
in baudrate-detect process.*/\r
#define UART_RXD_EDGE_CNT 0x000003FF\r
#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))\r
\r
#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)\r
/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to send xoff char�� it is cleared by hardware automatically.*/\r
+/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/\r
#define UART_SEND_XOFF (BIT(5))\r
#define UART_SEND_XOFF_M (BIT(5))\r
#define UART_SEND_XOFF_V 0x1\r
#define UART_SEND_XOFF_S 5\r
/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to send xon char�� it is cleared by hardware automatically.*/\r
+/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/\r
#define UART_SEND_XON (BIT(4))\r
#define UART_SEND_XON_M (BIT(4))\r
#define UART_SEND_XON_V 0x1\r
\r
#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)\r
/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */\r
-/*description: When the input rxd edge changes more than this register value��\r
+/*description: When the input rxd edge changes more than this register value.\r
the uart is active from light sleeping mode.*/\r
#define UART_ACTIVE_THRESHOLD 0x000003FF\r
#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))\r
#define UART_XON_CHAR_S 16\r
/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */\r
/*description: When the data amount in receiver's fifo is less than this register\r
- value�� it will send a xon char with uart_sw_flow_con_en set to 1.*/\r
+ value. it will send a xon char with uart_sw_flow_con_en set to 1.*/\r
#define UART_XOFF_THRESHOLD 0x000000FF\r
#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))\r
#define UART_XOFF_THRESHOLD_V 0xFF\r
#define UART_XOFF_THRESHOLD_S 8\r
/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */\r
/*description: when the data amount in receiver's fifo is more than this register\r
- value�� it will send a xoff char with uart_sw_flow_con_en set to 1.*/\r
+ value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/\r
#define UART_XON_THRESHOLD 0x000000FF\r
#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))\r
#define UART_XON_THRESHOLD_V 0xFF\r
#define UART_TX_IDLE_NUM_S 10\r
/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */\r
/*description: when receiver takes more time than this register value to receive\r
- a byte data�� it will produce frame end signal for uhci to stop receiving data.*/\r
+ a byte data. it will produce frame end signal for uhci to stop receiving data.*/\r
#define UART_RX_IDLE_THRHD 0x000003FF\r
#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))\r
#define UART_RX_IDLE_THRHD_V 0x3FF\r
#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)\r
/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */\r
/*description: This register is used to configure the idle duration time before\r
- the first at_cmd is received by receiver�� when the the duration is less than this register value it will not take the next data received as at_cmd char.*/\r
+ the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/\r
#define UART_PRE_IDLE_NUM 0x00FFFFFF\r
#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))\r
#define UART_PRE_IDLE_NUM_V 0xFFFFFF\r
#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)\r
/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */\r
/*description: This register is used to configure the duration time between\r
- the last at_cmd and the next data�� when the duration is less than this register value it will not take the previous data as at_cmd char.*/\r
+ the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/\r
#define UART_POST_IDLE_NUM 0x00FFFFFF\r
#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))\r
#define UART_POST_IDLE_NUM_V 0xFFFFFF\r
#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)\r
/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */\r
/*description: This register is used to configure the duration time between\r
- the at_cmd chars�� when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/\r
+ the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/\r
#define UART_RX_GAP_TOUT 0x00FFFFFF\r
#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))\r
#define UART_RX_GAP_TOUT_V 0xFFFFFF\r
#define UART_RX_SIZE_V 0xF\r
#define UART_RX_SIZE_S 3\r
/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to power down mem��when reg_mem_pd registers in\r
+/*description: Set this bit to power down mem.when reg_mem_pd registers in\r
the 3 uarts are all set to 1 mem will enter low power mode.*/\r
#define UART_MEM_PD (BIT(0))\r
#define UART_MEM_PD_M (BIT(0))\r
\r
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68)\r
/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
-/*description: This register stores the count of rxd posedge edge�� it is used\r
+/*description: This register stores the count of rxd posedge edge. it is used\r
in boudrate-detect process.*/\r
#define UART_POSEDGE_MIN_CNT 0x000FFFFF\r
#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))\r
\r
#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c)\r
/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
-/*description: This register stores the count of rxd negedge edge�� it is used\r
+/*description: This register stores the count of rxd negedge edge. it is used\r
in boudrate-detect process.*/\r
#define UART_NEGEDGE_MIN_CNT 0x000FFFFF\r
#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))\r
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