]> granicus.if.org Git - llvm/commitdiff
[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
authorAlex Bradbury <asb@lowrisc.org>
Mon, 11 Mar 2019 20:43:29 +0000 (20:43 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Mon, 11 Mar 2019 20:43:29 +0000 (20:43 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355864 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/RISCV/RISCVISelLowering.cpp
lib/Target/RISCV/RISCVInstrInfo.cpp

index 60041da06944ddae9394e944585224d5a00120ad..9b4193e53e1110b19ffa6f3dd3bffb6108951c43 100644 (file)
@@ -813,8 +813,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   F->insert(I, IfFalseMBB);
   F->insert(I, TailMBB);
   // Move all remaining instructions to TailMBB.
-  TailMBB->splice(TailMBB->begin(), HeadMBB,
-                  std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end());
+  TailMBB->splice(TailMBB->begin(), HeadMBB, std::next(MI.getIterator()),
+                  HeadMBB->end());
   // Update machine-CFG edges by transferring all successors of the current
   // block to the new block which will contain the Phi node for the select.
   TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
index ddb976b47fbc4dcd0e3ef3a3164e8c8837c953a6..dc63c51b4bc9ad3afe92a46b769054819bc632b1 100644 (file)
@@ -382,8 +382,8 @@ unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
       .addMBB(&DestBB, RISCVII::MO_LO);
 
   RS->enterBasicBlockEnd(MBB);
-  unsigned Scav = RS->scavengeRegisterBackwards(
-      RISCV::GPRRegClass, MachineBasicBlock::iterator(LuiMI), false, 0);
+  unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
+                                                LuiMI.getIterator(), false, 0);
   MRI.replaceRegWith(ScratchReg, Scav);
   MRI.clearVirtRegs();
   RS->setRegUsed(Scav);