[InstCombine] regenerate test checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311337 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstCombine/udivrem-change-width.ll b/test/Transforms/InstCombine/udivrem-change-width.ll
index 478e9ca387fca92d448b74d598c5eb20d8ed8f0a..b21855578866e9373d2f73d8e6b8d3fea50952c5 100644 (file)
--- a/test/Transforms/InstCombine/udivrem-change-width.ll
+++ b/test/Transforms/InstCombine/udivrem-change-width.ll
@@ -3,60 +3,73 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 
 ; PR4548
-define i8 @udiv_i8(i8 %a, i8 %b) nounwind {
-  %conv = zext i8 %a to i32       
-  %conv2 = zext i8 %b to i32      
-  %div = udiv i32 %conv, %conv2   
-  %conv3 = trunc i32 %div to i8   
-  ret i8 %conv3
+define i8 @udiv_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: @udiv_i8(
-; CHECK: udiv i8 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    ret i8 [[DIV]]
+;
+  %za = zext i8 %a to i32
+  %zb = zext i8 %b to i32
+  %udiv = udiv i32 %za, %zb
+  %conv3 = trunc i32 %udiv to i8
+  ret i8 %conv3
 }
 
-define i8 @urem_i8(i8 %a, i8 %b) nounwind {
-  %conv = zext i8 %a to i32       
-  %conv2 = zext i8 %b to i32      
-  %div = urem i32 %conv, %conv2   
-  %conv3 = trunc i32 %div to i8   
-  ret i8 %conv3
+define i8 @urem_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: @urem_i8(
-; CHECK: urem i8 %a, %b
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
+; CHECK-NEXT:    ret i8 [[TMP1]]
+;
+  %za = zext i8 %a to i32
+  %zb = zext i8 %b to i32
+  %udiv = urem i32 %za, %zb
+  %conv3 = trunc i32 %udiv to i8
+  ret i8 %conv3
 }
 
-define i32 @udiv_i32(i8 %a, i8 %b) nounwind {
-  %conv = zext i8 %a to i32
-  %conv2 = zext i8 %b to i32
-  %div = udiv i32 %conv, %conv2
-  ret i32 %div
+define i32 @udiv_i32(i8 %a, i8 %b) {
 ; CHECK-LABEL: @udiv_i32(
-; CHECK: udiv i8 %a, %b
-; CHECK: zext
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %za = zext i8 %a to i32
+  %zb = zext i8 %b to i32
+  %udiv = udiv i32 %za, %zb
+  ret i32 %udiv
 }
 
-define i32 @urem_i32(i8 %a, i8 %b) nounwind {
-  %conv = zext i8 %a to i32
-  %conv2 = zext i8 %b to i32
-  %div = urem i32 %conv, %conv2
-  ret i32 %div
+define i32 @urem_i32(i8 %a, i8 %b) {
 ; CHECK-LABEL: @urem_i32(
-; CHECK: urem i8 %a, %b
-; CHECK: zext
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %za = zext i8 %a to i32
+  %zb = zext i8 %b to i32
+  %udiv = urem i32 %za, %zb
+  ret i32 %udiv
 }
 
-define i32 @udiv_i32_c(i8 %a) nounwind {
-  %conv = zext i8 %a to i32
-  %div = udiv i32 %conv, 10
-  ret i32 %div
+define i32 @udiv_i32_c(i8 %a) {
 ; CHECK-LABEL: @udiv_i32_c(
-; CHECK: udiv i8 %a, 10
-; CHECK: zext
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, 10
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %za = zext i8 %a to i32
+  %udiv = udiv i32 %za, 10
+  ret i32 %udiv
 }
 
-define i32 @urem_i32_c(i8 %a) nounwind {
-  %conv = zext i8 %a to i32
-  %div = urem i32 %conv, 10
-  ret i32 %div
+define i32 @urem_i32_c(i8 %a) {
 ; CHECK-LABEL: @urem_i32_c(
-; CHECK: urem i8 %a, 10
-; CHECK: zext
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, 10
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %za = zext i8 %a to i32
+  %udiv = urem i32 %za, 10
+  ret i32 %udiv
 }
+