soc/rtc: fix spurious warnings about XTAL frequency on startup

1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
   before trying to use rtc_clk_cal_ratio.
   This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.

2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
   known. This reduces startup time after deep sleep or software reset.

3. Compare known XTAL frequency and estimated one before printing a
   warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
   (40MHz). Detected 40 MHz." warnings.

diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 049b47306a97b9deddde6899f72007351d2c1c89..612476cf8acb63e8bfac5eae37bae7319e6ebd5e 100644 (file)
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -558,6 +558,13 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
 
 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
 {
+    /* Enable 8M/256 clock if needed */
+    const bool clk_8m_enabled = rtc_clk_8m_enabled();
+    const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
+    if (!clk_8md256_enabled) {
+        rtc_clk_8m_enable(true, true);
+    }
+
     uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
     /* cal_val contains period of 8M/256 clock in XTAL clock cycles
      * (shifted by RTC_CLK_CAL_FRACT bits).
@@ -581,6 +588,8 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
             SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
             return RTC_XTAL_FREQ_AUTO;
     }
+    /* Restore 8M and 8md256 clocks to original state */
+    rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
 }
 
 void rtc_clk_apb_freq_update(uint32_t apb_freq)
@@ -634,7 +643,6 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
 
     /* Estimate XTAL frequency */
-    rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
     if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
         if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
@@ -642,7 +650,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
             xtal_freq = rtc_clk_xtal_freq_get();
         } else {
             /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
-            xtal_freq = est_xtal_freq;
+            xtal_freq = rtc_clk_xtal_freq_estimate();
             if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
                 SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
                 xtal_freq = RTC_XTAL_FREQ_26M;
@@ -653,8 +661,11 @@ void rtc_clk_init(rtc_clk_config_t cfg)
          * frequency is different. If autodetection failed, worst case we get a
          * bit of garbage output.
          */
-        SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
-                xtal_freq, est_xtal_freq);
+        rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
+        if (est_xtal_freq != xtal_freq) {
+            SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
+                    xtal_freq, est_xtal_freq);
+        }
     }
     uart_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);