[X86][FastISel] Fix lowering of overflow result on AVX512 targets

    Summary:
    Fix a case where the overflow value of type i1, which is legal on AVX512, was assigned to a VK1 register class.
    We always want this value to be assigned to a GPR since the overflow return value is lowered to a SETO instruction.

    Fixes pr30981.

    Reviewers: mkuper, igorb, craig.topper, guyblank, qcolombet

    Subscribers: qcolombet, llvm-commits

    Differential Revision: https://reviews.llvm.org/D26620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286958 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index d7eeb402b1dc646b716dcf9880a74d51aab686e7..a6dbf758466b090b44c0227c890ae7f22bc4e961 100644 (file)
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -2769,7 +2769,6 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
     const Function *Callee = II->getCalledFunction();
     auto *Ty = cast<StructType>(Callee->getReturnType());
     Type *RetTy = Ty->getTypeAtIndex(0U);
-    Type *CondTy = Ty->getTypeAtIndex(1);
 
     MVT VT;
     if (!isTypeLegal(RetTy, VT))
@@ -2879,7 +2878,8 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
     if (!ResultReg)
       return false;
 
-    unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
+    // Assign to a GPR since the overflow return value is lowered to a SETcc.
+    unsigned ResultReg2 = createResultReg(&X86::GR8RegClass);
     assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
             ResultReg2);

diff --git a/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll b/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
index d88b54a7edb94d029745a5afeb842594214d841e..4f8df0533aa393be0766ce163f4fed83f9067be6 100644 (file)
--- a/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
+++ b/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
@@ -10,14 +10,14 @@ declare %0 @llvm.sadd.with.overflow.i32(i32, i32) nounwind
 
 define fastcc i32 @test() nounwind {
 entry:
-; CHECK-LABEL: _test:
-; CHECK:      ## BB#0:
-; CHECK-NEXT: movl    $1, %eax
-; CHECK-NEXT: addl    $0, %eax
-; CHECK-NEXT: seto    %k0
-; CHECK-NEXT: movl    %eax, -4(%rsp)          ## 4-byte Spill
-; CHECK-NEXT: kmovw   %k0, -6(%rsp)           ## 2-byte Spill
-; CHECK-NEXT: jo      LBB0_2
+; CHECK-LABEL: test:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    addl $0, %eax
+; CHECK-NEXT:    seto %cl
+; CHECK-NEXT:    movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
+; CHECK-NEXT:    movb %cl, -{{[0-9]+}}(%rsp) ## 1-byte Spill
+; CHECK-NEXT:    jo LBB0_2
        %tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
        %tmp2 = extractvalue %0 %tmp1, 1
        br i1 %tmp2, label %.backedge, label %BB3