[DAGCombiner] Add general constant vector support to (shl (mul x, c1), c2) -> (mul...

We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284607 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9384d47b6413510471abc12a9807138f9b202625..a95099a2867f43bf9878a141ac3261e6d8429c03 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4678,11 +4678,12 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   }
 
   // fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
-  if (N1C && N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
-      if (SDValue Folded =
-              DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, N0C1, N1C))
-        return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Folded);
+  if (N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
+    if (isConstantOrConstantVector(N1, /* No Opaques */ true) &&
+        isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true)) {
+      SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
+      AddToWorklist(Shl.getNode());
+      return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl);
     }
   }
 

diff --git a/test/CodeGen/X86/combine-shl.ll b/test/CodeGen/X86/combine-shl.ll
index ff5d4f013a43fdff02c6c21295bc91260f1cc34d..dc3ca5e522932bc9ff456c5ba9138a08cbe9456f 100644 (file)
--- a/test/CodeGen/X86/combine-shl.ll
+++ b/test/CodeGen/X86/combine-shl.ll
@@ -572,7 +572,6 @@ define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) {
 ; AVX-LABEL: combine_vec_shl_mul1:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = mul <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
   %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>