2007-05-07 Hans Boehm <Hans.Boehm@hp.com> (with help from Philipp Zambelli)

	* src/atomic_ops/sysdeps/msftc/x86.h: Don't just assume that mfence
	is present.
	* src/atomic_ops/sysdeps/gcc/arm.h (AO_test_and_set_full): Correct
	oldval type.

2006-11-09 Earl Chew (Agilent)
	* msftc/x86.h: Follow Microsoft documentation and include
	windows.h.

diff --git a/ChangeLog b/ChangeLog
index 9d05e5cb56da07862bd36802f2d2b2864d243a49..a1f6ba9a91ac1330224d2b959a708eae96c5ebb1 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,13 @@
+2007-05-07  Hans Boehm <Hans.Boehm@hp.com> (with help from Philipp Zambelli)
+       * src/atomic_ops/sysdeps/msftc/x86.h: Don't just assume that mfence
+       is present.
+       * src/atomic_ops/sysdeps/gcc/arm.h (AO_test_and_set_full): Correct
+       oldval type.
+
+2006-11-09 Earl Chew (Agilent)
+       * msftc/x86.h: Follow Microsoft documentation and include
+       windows.h.
+
 [1.2 release]
 
 2006-07-11 Hans Boehm <Hans.Boehm@hp.com>

diff --git a/src/atomic_ops/sysdeps/gcc/arm.h b/src/atomic_ops/sysdeps/gcc/arm.h
index 9548a32b0e0e5ba177676fa17a3b1dbeb226b59b..d1a323216db1c6b7538f9d25b0589f9f664217d3 100644 (file)
--- a/src/atomic_ops/sysdeps/gcc/arm.h
+++ b/src/atomic_ops/sysdeps/gcc/arm.h
@@ -15,8 +15,8 @@
  *
  */
 
-/* There exist multiprocessor SoC ARM processors, so this may actually */
-/* matter.                                                             */
+/* There exist multiprocessor SoC ARM processors, so this matters.     */
+/* This needs to be augmented for later ARM (e.g. V7) procesors.       */
 
 /* I found a slide set that, if I read it correctly, claims that       */
 /* Loads followed by either a Load or Store are ordered, but nothing   */
@@ -31,7 +31,7 @@
 
 AO_INLINE AO_TS_VAL_t
 AO_test_and_set_full(volatile AO_TS_t *addr) {
-  int oldval;
+  AO_TS_VAL_t oldval;
   /* SWP on ARM is very similar to XCHG on x86.                */
   /* The first operand is the result, the second the value     */
   /* to be stored.  Both registers must be different from addr.        */

diff --git a/src/atomic_ops/sysdeps/msftc/x86.h b/src/atomic_ops/sysdeps/msftc/x86.h
index 1192d90e18691a64aa0a75f656103e723201c00e..2376d0c205783866cfdeb6807479b7878e67c675 100644 (file)
--- a/src/atomic_ops/sysdeps/msftc/x86.h
+++ b/src/atomic_ops/sysdeps/msftc/x86.h
@@ -36,7 +36,9 @@
 
 #include "../test_and_set_t_is_char.h"
 
-#include <winbase.h>
+#include <windows.h>
+       /* Seems like over-kill, but that's what MSDN recommends.       */
+       /* And apparently winbase.h is not always self-contained.       */
 
 #if _MSC_VER < 1310
 
@@ -80,6 +82,12 @@ LONG __cdecl _InterlockedCompareExchange(LONG volatile* Dest,
 /* As far as we can tell, the lfence and sfence instructions are not   */
 /* currently needed or useful for cached memory accesses.              */
 
+/* Unfortunately mfence doesn't exist everywhere.              */
+/* IsProcessorFeaturePresent(PF_COMPARE_EXCHANGE128) is                */
+/* probably a conservative test for it?                                */
+
+#if defined(AO_USE_PENTIUM4_INSTRS)
+
 AO_INLINE void
 AO_nop_full()
 {
@@ -88,6 +96,14 @@ AO_nop_full()
 
 #define AO_HAVE_nop_full
 
+#else
+
+/* We could use the cpuid instruction.  But that seems to be slower    */
+/* than the default implementation based on test_and_set_full.  Thus   */
+/* we omit that bit of misinformation here.                            */
+
+#endif
+
 AO_INLINE AO_t
 AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
 {