virtual ~MCWinCOFFObjectTargetWriter() = default;
unsigned getMachine() const { return Machine; }
- virtual unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup,
- bool IsCrossSection,
+ virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
+ const MCFixup &Fixup, bool IsCrossSection,
const MCAsmBackend &MAB) const = 0;
virtual bool recordRelocation(const MCFixup &) const { return true; }
};
++Reloc.Symb->Relocations;
Reloc.Data.VirtualAddress += Fixup.getOffset();
- Reloc.Data.Type =
- TargetObjectWriter->getRelocType(Target, Fixup, SymB, Asm.getBackend());
+ Reloc.Data.Type = TargetObjectWriter->getRelocType(
+ Asm.getContext(), Target, Fixup, SymB, Asm.getBackend());
// FIXME: Can anyone explain what this does other than adjust for the size
// of the offset?
~ARMWinCOFFObjectWriter() override = default;
- unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup,
- bool IsCrossSection,
+ unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
+ const MCFixup &Fixup, bool IsCrossSection,
const MCAsmBackend &MAB) const override;
bool recordRelocation(const MCFixup &) const override;
} // end anonymous namespace
-unsigned ARMWinCOFFObjectWriter::getRelocType(const MCValue &Target,
+unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
+ const MCValue &Target,
const MCFixup &Fixup,
bool IsCrossSection,
const MCAsmBackend &MAB) const {
#include "MCTargetDesc/X86FixupKinds.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/BinaryFormat/COFF.h"
+#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCValue.h"
X86WinCOFFObjectWriter(bool Is64Bit);
~X86WinCOFFObjectWriter() override = default;
- unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup,
- bool IsCrossSection,
+ unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
+ const MCFixup &Fixup, bool IsCrossSection,
const MCAsmBackend &MAB) const override;
};
: MCWinCOFFObjectTargetWriter(Is64Bit ? COFF::IMAGE_FILE_MACHINE_AMD64
: COFF::IMAGE_FILE_MACHINE_I386) {}
-unsigned X86WinCOFFObjectWriter::getRelocType(const MCValue &Target,
+unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
+ const MCValue &Target,
const MCFixup &Fixup,
bool IsCrossSection,
const MCAsmBackend &MAB) const {
- unsigned FixupKind = IsCrossSection ? FK_PCRel_4 : Fixup.getKind();
+ unsigned FixupKind = Fixup.getKind();
+ if (IsCrossSection) {
+ if (FixupKind != FK_Data_4) {
+ Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
+ return COFF::IMAGE_REL_AMD64_ADDR32;
+ }
+ FixupKind = FK_PCRel_4;
+ }
MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
--- /dev/null
+// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-win32 %s -o /dev/null 2>&1 | FileCheck %s
+
+
+// CHECK: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
+ .byte foo - .
+
+// CHECK: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
+ .short foo - .
+
+// CHECK: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
+ .quad foo - .
+
.globl t1 # @t1
.align 8
t1:
- .quad (g3-t1)+4
.globl t2 # @t2
.align 8
t2:
- .quad g3-t2
.globl t3 # @t3
.align 8
t3:
- .quad (g3-t3)-4
.globl t4 # @t4
.align 4
// READOBJ-NEXT: IMAGE_SCN_MEM_WRITE (0x80000000)
// READOBJ-NEXT: ]
// READOBJ-NEXT: SectionData (
-// READOBJ-NEXT: 0000: 08000000 00000000 04000000 00000000 |
-// READOBJ-NEXT: 0010: 00000000 00000000 04000000 00000000 |
-// READOBJ-NEXT: 0020: 01020000 00000000 00010000 00000000 |
-// READOBJ-NEXT: 0030: 04000000 00000000 04000000 |
+// READOBJ-NEXT: 0000: 04000000 00000000 00000000 00000000 |
+// READOBJ-NEXT: 0010: 01020000 00000000 00010000 00000000 |
+// READOBJ-NEXT: 0020: 04000000 00000000 04000000 |
// READOBJ-NEXT: )
// READOBJ-NEXT: }
// READOBJ-NEXT: ]
// READOBJ-NEXT: Symbol: g3
// READOBJ-NEXT: }
// READOBJ-NEXT: Relocation {
-// READOBJ-NEXT: Offset: 0x8
-// READOBJ-NEXT: Type: IMAGE_REL_AMD64_REL32 (4)
-// READOBJ-NEXT: Symbol: g3
-// READOBJ-NEXT: }
-// READOBJ-NEXT: Relocation {
-// READOBJ-NEXT: Offset: 0x10
-// READOBJ-NEXT: Type: IMAGE_REL_AMD64_REL32 (4)
-// READOBJ-NEXT: Symbol: g3
-// READOBJ-NEXT: }
-// READOBJ-NEXT: Relocation {
-// READOBJ-NEXT: Offset: 0x18
-// READOBJ-NEXT: Type: IMAGE_REL_AMD64_REL32 (4)
-// READOBJ-NEXT: Symbol: g3
-// READOBJ-NEXT: }
-// READOBJ-NEXT: Relocation {
-// READOBJ-NEXT: Offset: 0x1C
+// READOBJ-NEXT: Offset: 0x4
// READOBJ-NEXT: Type: IMAGE_REL_AMD64_ADDR32NB (3)
// READOBJ-NEXT: Symbol: g3
// READOBJ-NEXT: }
// READOBJ-NEXT: Relocation {
-// READOBJ-NEXT: Offset: 0x30
+// READOBJ-NEXT: Offset: 0x20
// READOBJ-NEXT: Type: IMAGE_REL_AMD64_REL32 (4)
// READOBJ-NEXT: Symbol: g3
// READOBJ-NEXT: }
// READOBJ-NEXT: Relocation {
-// READOBJ-NEXT: Offset: 0x38
+// READOBJ-NEXT: Offset: 0x28
// READOBJ-NEXT: Type: IMAGE_REL_AMD64_REL32 (4)
// READOBJ-NEXT: Symbol: foobar
// READOBJ-NEXT: }