[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated frame pointer. The changes in
callee-saved-gprs.ll most clearly show the effect of this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356063 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/RISCV/RISCVRegisterInfo.cpp b/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 75ab0a4d4447bda4f57e40643f221bf2239338f4..38af3827e4ca2128e1823890db7fc2632e3872b1 100644 (file)
--- a/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -43,6 +43,7 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 }
 
 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+  const TargetFrameLowering *TFI = getFrameLowering(MF);
   BitVector Reserved(getNumRegs());
 
   // Use markSuperRegs to ensure any register aliases are also reserved
@@ -51,7 +52,8 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, RISCV::X2); // sp
   markSuperRegs(Reserved, RISCV::X3); // gp
   markSuperRegs(Reserved, RISCV::X4); // tp
-  markSuperRegs(Reserved, RISCV::X8); // fp
+  if (TFI->hasFP(MF))
+    markSuperRegs(Reserved, RISCV::X8); // fp
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }

diff --git a/test/CodeGen/RISCV/atomic-rmw.ll b/test/CodeGen/RISCV/atomic-rmw.ll
index 9e98af6037c763e8104d4f2b6b7928f38ed8563c..407b0791f47eb450b8d92dcb15549294e8e0fc23 100644 (file)
--- a/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/test/CodeGen/RISCV/atomic-rmw.ll
@@ -2073,29 +2073,29 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB35_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB35_3
+; RV32I-NEXT:    blt s0, a1, .LBB35_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB35_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
@@ -2104,10 +2104,10 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB35_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -2146,29 +2146,29 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB35_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB35_3
+; RV64I-NEXT:    blt s0, a1, .LBB35_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB35_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -2177,10 +2177,10 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB35_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -2223,29 +2223,29 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB36_3
+; RV32I-NEXT:    blt s0, a1, .LBB36_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB36_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -2254,10 +2254,10 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB36_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -2296,29 +2296,29 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB36_3
+; RV64I-NEXT:    blt s0, a1, .LBB36_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB36_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -2327,10 +2327,10 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB36_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -2373,29 +2373,29 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB37_3
+; RV32I-NEXT:    blt s0, a1, .LBB37_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB37_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
@@ -2404,10 +2404,10 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB37_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -2446,29 +2446,29 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB37_3
+; RV64I-NEXT:    blt s0, a1, .LBB37_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB37_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -2477,10 +2477,10 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB37_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -2523,29 +2523,29 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB38_3
+; RV32I-NEXT:    blt s0, a1, .LBB38_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB38_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -2554,10 +2554,10 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB38_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -2596,29 +2596,29 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB38_3
+; RV64I-NEXT:    blt s0, a1, .LBB38_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB38_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -2627,10 +2627,10 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB38_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -2673,29 +2673,29 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB39_3
+; RV32I-NEXT:    blt s0, a1, .LBB39_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB39_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
@@ -2704,10 +2704,10 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB39_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -2746,29 +2746,29 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB39_3
+; RV64I-NEXT:    blt s0, a1, .LBB39_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB39_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -2777,10 +2777,10 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB39_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -2823,29 +2823,29 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB40_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB40_3
+; RV32I-NEXT:    bge s0, a1, .LBB40_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB40_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
@@ -2854,10 +2854,10 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB40_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -2896,29 +2896,29 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB40_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB40_3
+; RV64I-NEXT:    bge s0, a1, .LBB40_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB40_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -2927,10 +2927,10 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB40_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -2973,29 +2973,29 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB41_3
+; RV32I-NEXT:    bge s0, a1, .LBB41_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB41_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -3004,10 +3004,10 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB41_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3046,29 +3046,29 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB41_3
+; RV64I-NEXT:    bge s0, a1, .LBB41_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB41_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -3077,10 +3077,10 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB41_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3123,29 +3123,29 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB42_3
+; RV32I-NEXT:    bge s0, a1, .LBB42_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB42_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
@@ -3154,10 +3154,10 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB42_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3196,29 +3196,29 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB42_3
+; RV64I-NEXT:    bge s0, a1, .LBB42_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB42_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -3227,10 +3227,10 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB42_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3273,29 +3273,29 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB43_3
+; RV32I-NEXT:    bge s0, a1, .LBB43_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB43_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -3304,10 +3304,10 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB43_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3346,29 +3346,29 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB43_3
+; RV64I-NEXT:    bge s0, a1, .LBB43_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB43_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -3377,10 +3377,10 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB43_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3423,29 +3423,29 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    srai s0, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB44_3
+; RV32I-NEXT:    bge s0, a1, .LBB44_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB44_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
@@ -3454,10 +3454,10 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB44_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3496,29 +3496,29 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    srai s0, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB44_3
+; RV64I-NEXT:    bge s0, a1, .LBB44_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB44_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -3527,10 +3527,10 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB44_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3573,27 +3573,27 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB45_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s1, a1, .LBB45_3
+; RV32I-NEXT:    bltu s0, a1, .LBB45_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB45_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB45_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB45_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
@@ -3602,10 +3602,10 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB45_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3639,27 +3639,27 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB45_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB45_3
+; RV64I-NEXT:    bltu s0, a1, .LBB45_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB45_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB45_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB45_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -3668,10 +3668,10 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB45_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3709,27 +3709,27 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB46_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s1, a1, .LBB46_3
+; RV32I-NEXT:    bltu s0, a1, .LBB46_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB46_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB46_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB46_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -3738,10 +3738,10 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB46_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3775,27 +3775,27 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB46_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB46_3
+; RV64I-NEXT:    bltu s0, a1, .LBB46_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB46_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB46_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB46_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -3804,10 +3804,10 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB46_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3845,27 +3845,27 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB47_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s1, a1, .LBB47_3
+; RV32I-NEXT:    bltu s0, a1, .LBB47_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB47_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB47_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB47_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
@@ -3874,10 +3874,10 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB47_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -3911,27 +3911,27 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB47_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB47_3
+; RV64I-NEXT:    bltu s0, a1, .LBB47_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB47_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB47_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB47_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -3940,10 +3940,10 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB47_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -3981,27 +3981,27 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB48_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s1, a1, .LBB48_3
+; RV32I-NEXT:    bltu s0, a1, .LBB48_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB48_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB48_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB48_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -4010,10 +4010,10 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB48_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4047,27 +4047,27 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB48_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB48_3
+; RV64I-NEXT:    bltu s0, a1, .LBB48_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB48_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB48_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB48_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -4076,10 +4076,10 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB48_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -4117,27 +4117,27 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s1, a1, .LBB49_3
+; RV32I-NEXT:    bltu s0, a1, .LBB49_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB49_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB49_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB49_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
@@ -4146,10 +4146,10 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB49_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4183,27 +4183,27 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB49_3
+; RV64I-NEXT:    bltu s0, a1, .LBB49_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB49_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB49_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB49_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -4212,10 +4212,10 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB49_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -4253,27 +4253,27 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB50_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s1, a1, .LBB50_3
+; RV32I-NEXT:    bgeu s0, a1, .LBB50_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB50_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB50_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB50_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
@@ -4282,10 +4282,10 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB50_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4319,27 +4319,27 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB50_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB50_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB50_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB50_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB50_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB50_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -4348,10 +4348,10 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB50_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -4389,27 +4389,27 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s1, a1, .LBB51_3
+; RV32I-NEXT:    bgeu s0, a1, .LBB51_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB51_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB51_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB51_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -4418,10 +4418,10 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB51_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4455,27 +4455,27 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB51_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB51_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB51_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB51_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB51_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -4484,10 +4484,10 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB51_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -4525,27 +4525,27 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s1, a1, .LBB52_3
+; RV32I-NEXT:    bgeu s0, a1, .LBB52_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB52_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB52_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB52_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
@@ -4554,10 +4554,10 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB52_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4591,27 +4591,27 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB52_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB52_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB52_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB52_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB52_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -4620,10 +4620,10 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB52_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -4661,27 +4661,27 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB53_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s1, a1, .LBB53_3
+; RV32I-NEXT:    bgeu s0, a1, .LBB53_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB53_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB53_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB53_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -4690,10 +4690,10 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB53_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4727,27 +4727,27 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB53_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB53_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB53_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB53_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB53_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB53_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -4756,10 +4756,10 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB53_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -4797,27 +4797,27 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    andi s0, a1, 255
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB54_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s1, a1, .LBB54_3
+; RV32I-NEXT:    bgeu s0, a1, .LBB54_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB54_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB54_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB54_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
@@ -4826,10 +4826,10 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB54_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -4863,27 +4863,27 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    andi s0, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB54_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB54_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB54_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB54_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB54_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB54_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -4892,10 +4892,10 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB54_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7083,29 +7083,29 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB90_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB90_3
+; RV32I-NEXT:    blt s0, a1, .LBB90_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB90_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB90_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB90_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
@@ -7114,10 +7114,10 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB90_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -7157,29 +7157,29 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB90_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB90_3
+; RV64I-NEXT:    blt s0, a1, .LBB90_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB90_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB90_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB90_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -7188,10 +7188,10 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB90_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7235,29 +7235,29 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB91_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB91_3
+; RV32I-NEXT:    blt s0, a1, .LBB91_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB91_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB91_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB91_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -7266,10 +7266,10 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB91_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -7309,29 +7309,29 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB91_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB91_3
+; RV64I-NEXT:    blt s0, a1, .LBB91_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB91_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB91_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB91_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -7340,10 +7340,10 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB91_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7387,29 +7387,29 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB92_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB92_3
+; RV32I-NEXT:    blt s0, a1, .LBB92_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB92_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB92_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB92_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
@@ -7418,10 +7418,10 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB92_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -7461,29 +7461,29 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB92_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB92_3
+; RV64I-NEXT:    blt s0, a1, .LBB92_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB92_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB92_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB92_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -7492,10 +7492,10 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB92_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7539,29 +7539,29 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB93_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB93_3
+; RV32I-NEXT:    blt s0, a1, .LBB93_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB93_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB93_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB93_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -7570,10 +7570,10 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB93_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -7613,29 +7613,29 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB93_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB93_3
+; RV64I-NEXT:    blt s0, a1, .LBB93_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB93_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB93_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB93_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -7644,10 +7644,10 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB93_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7691,29 +7691,29 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB94_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s1, a1, .LBB94_3
+; RV32I-NEXT:    blt s0, a1, .LBB94_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB94_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB94_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB94_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
@@ -7722,10 +7722,10 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB94_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -7765,29 +7765,29 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB94_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB94_3
+; RV64I-NEXT:    blt s0, a1, .LBB94_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB94_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB94_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB94_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -7796,10 +7796,10 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB94_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7843,29 +7843,29 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB95_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB95_3
+; RV32I-NEXT:    bge s0, a1, .LBB95_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB95_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB95_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB95_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
@@ -7874,10 +7874,10 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB95_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -7917,29 +7917,29 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB95_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB95_3
+; RV64I-NEXT:    bge s0, a1, .LBB95_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB95_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB95_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB95_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -7948,10 +7948,10 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB95_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -7995,29 +7995,29 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB96_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB96_3
+; RV32I-NEXT:    bge s0, a1, .LBB96_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB96_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB96_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB96_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -8026,10 +8026,10 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB96_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8069,29 +8069,29 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB96_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB96_3
+; RV64I-NEXT:    bge s0, a1, .LBB96_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB96_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB96_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB96_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -8100,10 +8100,10 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB96_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -8147,29 +8147,29 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB97_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB97_3
+; RV32I-NEXT:    bge s0, a1, .LBB97_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB97_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB97_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB97_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
@@ -8178,10 +8178,10 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB97_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8221,29 +8221,29 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB97_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB97_3
+; RV64I-NEXT:    bge s0, a1, .LBB97_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB97_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB97_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB97_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -8252,10 +8252,10 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB97_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -8299,29 +8299,29 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB98_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB98_3
+; RV32I-NEXT:    bge s0, a1, .LBB98_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB98_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB98_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB98_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
@@ -8330,10 +8330,10 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB98_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8373,29 +8373,29 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB98_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB98_3
+; RV64I-NEXT:    bge s0, a1, .LBB98_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB98_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB98_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB98_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -8404,10 +8404,10 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB98_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -8451,29 +8451,29 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    srai s0, a1, 16
 ; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB99_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s1, a1, .LBB99_3
+; RV32I-NEXT:    bge s0, a1, .LBB99_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB99_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB99_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB99_1 Depth=1
 ; RV32I-NEXT:    sh a0, 10(sp)
-; RV32I-NEXT:    mv a0, s4
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
@@ -8482,10 +8482,10 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB99_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8525,29 +8525,29 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    srai s0, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB99_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB99_3
+; RV64I-NEXT:    bge s0, a1, .LBB99_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB99_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB99_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB99_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -8556,10 +8556,10 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB99_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -8603,23 +8603,23 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB100_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB100_3
+; RV32I-NEXT:    bltu s1, a1, .LBB100_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB100_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -8635,11 +8635,11 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB100_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8674,23 +8674,23 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB100_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB100_3
+; RV64I-NEXT:    bltu s1, a1, .LBB100_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB100_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -8706,11 +8706,11 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB100_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -8749,23 +8749,23 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB101_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB101_3
+; RV32I-NEXT:    bltu s1, a1, .LBB101_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB101_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -8781,11 +8781,11 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB101_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8820,23 +8820,23 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB101_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB101_3
+; RV64I-NEXT:    bltu s1, a1, .LBB101_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB101_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -8852,11 +8852,11 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB101_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -8895,23 +8895,23 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB102_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB102_3
+; RV32I-NEXT:    bltu s1, a1, .LBB102_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB102_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -8927,11 +8927,11 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB102_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -8966,23 +8966,23 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB102_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB102_3
+; RV64I-NEXT:    bltu s1, a1, .LBB102_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB102_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -8998,11 +8998,11 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB102_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9041,23 +9041,23 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB103_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB103_3
+; RV32I-NEXT:    bltu s1, a1, .LBB103_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB103_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9073,11 +9073,11 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB103_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9112,23 +9112,23 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB103_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB103_3
+; RV64I-NEXT:    bltu s1, a1, .LBB103_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB103_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -9144,11 +9144,11 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB103_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9187,23 +9187,23 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB104_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB104_3
+; RV32I-NEXT:    bltu s1, a1, .LBB104_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB104_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9219,11 +9219,11 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB104_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9258,23 +9258,23 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB104_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB104_3
+; RV64I-NEXT:    bltu s1, a1, .LBB104_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB104_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -9290,11 +9290,11 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB104_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9333,23 +9333,23 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB105_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB105_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB105_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB105_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9365,11 +9365,11 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB105_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9404,23 +9404,23 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB105_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB105_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB105_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB105_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -9436,11 +9436,11 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB105_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9479,23 +9479,23 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB106_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB106_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB106_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB106_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9511,11 +9511,11 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB106_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9550,23 +9550,23 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB106_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB106_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB106_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB106_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -9582,11 +9582,11 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB106_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9625,23 +9625,23 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB107_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB107_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB107_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB107_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9657,11 +9657,11 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB107_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9696,23 +9696,23 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB107_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB107_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB107_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB107_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -9728,11 +9728,11 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB107_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9771,23 +9771,23 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB108_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB108_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB108_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB108_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9803,11 +9803,11 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB108_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9842,23 +9842,23 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB108_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB108_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB108_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB108_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -9874,11 +9874,11 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB108_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -9917,23 +9917,23 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s0, a1, -1
+; RV32I-NEXT:    and s1, s2, s0
 ; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB109_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB109_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB109_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB109_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
@@ -9949,11 +9949,11 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB109_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -9988,23 +9988,23 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
+; RV64I-NEXT:    sd s2, 32(sp)
+; RV64I-NEXT:    sd s3, 24(sp)
+; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addiw s0, a1, -1
+; RV64I-NEXT:    and s1, s2, s0
 ; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB109_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    and a1, a0, s0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB109_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB109_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB109_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
@@ -10020,11 +10020,11 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB109_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld s4, 16(sp)
+; RV64I-NEXT:    ld s3, 24(sp)
+; RV64I-NEXT:    ld s2, 32(sp)
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
@@ -11333,24 +11333,24 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB145_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    blt s1, a2, .LBB145_3
+; RV32I-NEXT:    blt s0, a2, .LBB145_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB145_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB145_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB145_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11358,9 +11358,9 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB145_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11374,27 +11374,27 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB145_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB145_3
+; RV64I-NEXT:    blt s0, a1, .LBB145_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB145_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB145_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB145_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -11403,10 +11403,10 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB145_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11424,24 +11424,24 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB146_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    blt s1, a2, .LBB146_3
+; RV32I-NEXT:    blt s0, a2, .LBB146_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB146_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB146_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB146_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11449,9 +11449,9 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB146_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11465,27 +11465,27 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB146_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB146_3
+; RV64I-NEXT:    blt s0, a1, .LBB146_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB146_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB146_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB146_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -11494,10 +11494,10 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB146_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11515,24 +11515,24 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB147_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    blt s1, a2, .LBB147_3
+; RV32I-NEXT:    blt s0, a2, .LBB147_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB147_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB147_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB147_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11540,9 +11540,9 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB147_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11556,27 +11556,27 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB147_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB147_3
+; RV64I-NEXT:    blt s0, a1, .LBB147_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB147_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB147_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB147_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -11585,10 +11585,10 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB147_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11606,24 +11606,24 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB148_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    blt s1, a2, .LBB148_3
+; RV32I-NEXT:    blt s0, a2, .LBB148_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB148_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB148_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB148_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11631,9 +11631,9 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB148_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11647,27 +11647,27 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB148_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB148_3
+; RV64I-NEXT:    blt s0, a1, .LBB148_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB148_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB148_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB148_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -11676,10 +11676,10 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB148_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11697,24 +11697,24 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB149_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    blt s1, a2, .LBB149_3
+; RV32I-NEXT:    blt s0, a2, .LBB149_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB149_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB149_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB149_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11722,9 +11722,9 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB149_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11738,27 +11738,27 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB149_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s1, a1, .LBB149_3
+; RV64I-NEXT:    blt s0, a1, .LBB149_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB149_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB149_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB149_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -11767,10 +11767,10 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB149_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11788,24 +11788,24 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB150_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bge s1, a2, .LBB150_3
+; RV32I-NEXT:    bge s0, a2, .LBB150_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB150_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB150_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB150_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11813,9 +11813,9 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB150_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11829,27 +11829,27 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB150_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB150_3
+; RV64I-NEXT:    bge s0, a1, .LBB150_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB150_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB150_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB150_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -11858,10 +11858,10 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB150_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11879,24 +11879,24 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB151_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bge s1, a2, .LBB151_3
+; RV32I-NEXT:    bge s0, a2, .LBB151_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB151_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB151_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB151_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11904,9 +11904,9 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB151_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -11920,27 +11920,27 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB151_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB151_3
+; RV64I-NEXT:    bge s0, a1, .LBB151_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB151_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB151_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB151_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -11949,10 +11949,10 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB151_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -11970,24 +11970,24 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB152_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bge s1, a2, .LBB152_3
+; RV32I-NEXT:    bge s0, a2, .LBB152_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB152_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB152_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB152_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -11995,9 +11995,9 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB152_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12011,27 +12011,27 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB152_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB152_3
+; RV64I-NEXT:    bge s0, a1, .LBB152_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB152_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB152_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB152_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -12040,10 +12040,10 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB152_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12061,24 +12061,24 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB153_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bge s1, a2, .LBB153_3
+; RV32I-NEXT:    bge s0, a2, .LBB153_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB153_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB153_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB153_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12086,9 +12086,9 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB153_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12102,27 +12102,27 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB153_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB153_3
+; RV64I-NEXT:    bge s0, a1, .LBB153_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB153_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB153_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB153_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -12131,10 +12131,10 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB153_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12152,24 +12152,24 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB154_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bge s1, a2, .LBB154_3
+; RV32I-NEXT:    bge s0, a2, .LBB154_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB154_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB154_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB154_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12177,9 +12177,9 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB154_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12193,27 +12193,27 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB154_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s1, a1, .LBB154_3
+; RV64I-NEXT:    bge s0, a1, .LBB154_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB154_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB154_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB154_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -12222,10 +12222,10 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB154_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12243,24 +12243,24 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB155_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bltu s1, a2, .LBB155_3
+; RV32I-NEXT:    bltu s0, a2, .LBB155_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB155_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB155_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB155_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12268,9 +12268,9 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB155_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12284,27 +12284,27 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB155_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB155_3
+; RV64I-NEXT:    bltu s0, a1, .LBB155_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB155_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB155_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB155_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -12313,10 +12313,10 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB155_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12334,24 +12334,24 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB156_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bltu s1, a2, .LBB156_3
+; RV32I-NEXT:    bltu s0, a2, .LBB156_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB156_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB156_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB156_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12359,9 +12359,9 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB156_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12375,27 +12375,27 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB156_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB156_3
+; RV64I-NEXT:    bltu s0, a1, .LBB156_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB156_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB156_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB156_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -12404,10 +12404,10 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB156_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12425,24 +12425,24 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB157_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bltu s1, a2, .LBB157_3
+; RV32I-NEXT:    bltu s0, a2, .LBB157_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB157_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB157_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB157_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12450,9 +12450,9 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB157_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12466,27 +12466,27 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB157_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB157_3
+; RV64I-NEXT:    bltu s0, a1, .LBB157_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB157_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB157_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB157_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -12495,10 +12495,10 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB157_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12516,24 +12516,24 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB158_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bltu s1, a2, .LBB158_3
+; RV32I-NEXT:    bltu s0, a2, .LBB158_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB158_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB158_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB158_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12541,9 +12541,9 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB158_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12557,27 +12557,27 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB158_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB158_3
+; RV64I-NEXT:    bltu s0, a1, .LBB158_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB158_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB158_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB158_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -12586,10 +12586,10 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB158_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12607,24 +12607,24 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB159_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bltu s1, a2, .LBB159_3
+; RV32I-NEXT:    bltu s0, a2, .LBB159_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB159_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB159_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB159_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12632,9 +12632,9 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB159_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12648,27 +12648,27 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB159_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s1, a1, .LBB159_3
+; RV64I-NEXT:    bltu s0, a1, .LBB159_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB159_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB159_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB159_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -12677,10 +12677,10 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB159_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12698,24 +12698,24 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB160_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bgeu s1, a2, .LBB160_3
+; RV32I-NEXT:    bgeu s0, a2, .LBB160_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB160_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB160_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB160_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12723,9 +12723,9 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB160_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12739,27 +12739,27 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB160_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB160_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB160_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB160_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB160_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB160_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
@@ -12768,10 +12768,10 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB160_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12789,24 +12789,24 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB161_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bgeu s1, a2, .LBB161_3
+; RV32I-NEXT:    bgeu s0, a2, .LBB161_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB161_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB161_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB161_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12814,9 +12814,9 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB161_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12830,27 +12830,27 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB161_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB161_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB161_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB161_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB161_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB161_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -12859,10 +12859,10 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB161_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12880,24 +12880,24 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB162_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bgeu s1, a2, .LBB162_3
+; RV32I-NEXT:    bgeu s0, a2, .LBB162_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB162_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB162_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB162_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12905,9 +12905,9 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB162_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -12921,27 +12921,27 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB162_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB162_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB162_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB162_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB162_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB162_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
@@ -12950,10 +12950,10 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB162_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -12971,24 +12971,24 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB163_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bgeu s1, a2, .LBB163_3
+; RV32I-NEXT:    bgeu s0, a2, .LBB163_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB163_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB163_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB163_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -12996,9 +12996,9 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB163_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -13012,27 +13012,27 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB163_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB163_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB163_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB163_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB163_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB163_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
@@ -13041,10 +13041,10 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB163_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -13062,24 +13062,24 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    mv s0, a1
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 12
+; RV32I-NEXT:    addi s2, sp, 12
 ; RV32I-NEXT:  .LBB164_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    bgeu s1, a2, .LBB164_3
+; RV32I-NEXT:    bgeu s0, a2, .LBB164_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB164_1 Depth=1
-; RV32I-NEXT:    mv a2, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:  .LBB164_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB164_1 Depth=1
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
@@ -13087,9 +13087,9 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB164_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -13103,27 +13103,27 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    sd s3, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    sext.w s0, a1
 ; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB164_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s1, a1, .LBB164_3
+; RV64I-NEXT:    bgeu s0, a1, .LBB164_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB164_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB164_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB164_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
@@ -13132,10 +13132,10 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB164_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s4, 8(sp)
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s3, 8(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -14558,22 +14558,22 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB200_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB200_3
+; RV32I-NEXT:    beq a1, s0, .LBB200_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB200_4
 ; RV32I-NEXT:    j .LBB200_5
@@ -14590,12 +14590,12 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB200_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB200_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -14604,10 +14604,10 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB200_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -14616,22 +14616,22 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB200_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB200_3
+; RV32IA-NEXT:    beq a1, s0, .LBB200_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB200_4
 ; RV32IA-NEXT:    j .LBB200_5
@@ -14648,12 +14648,12 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB200_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB200_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    mv a4, zero
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -14662,10 +14662,10 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB200_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -14674,24 +14674,24 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB200_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    blt s1, a2, .LBB200_3
+; RV64I-NEXT:    blt s0, a2, .LBB200_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB200_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB200_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB200_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -14699,9 +14699,9 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB200_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -14719,22 +14719,22 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB201_3
+; RV32I-NEXT:    beq a1, s0, .LBB201_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB201_4
 ; RV32I-NEXT:    j .LBB201_5
@@ -14751,12 +14751,12 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB201_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB201_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -14765,10 +14765,10 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB201_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -14777,22 +14777,22 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB201_3
+; RV32IA-NEXT:    beq a1, s0, .LBB201_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB201_4
 ; RV32IA-NEXT:    j .LBB201_5
@@ -14809,12 +14809,12 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB201_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB201_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 2
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -14823,10 +14823,10 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB201_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -14835,24 +14835,24 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    blt s1, a2, .LBB201_3
+; RV64I-NEXT:    blt s0, a2, .LBB201_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB201_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB201_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB201_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -14860,9 +14860,9 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB201_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -14880,22 +14880,22 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB202_3
+; RV32I-NEXT:    beq a1, s0, .LBB202_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB202_4
 ; RV32I-NEXT:    j .LBB202_5
@@ -14912,12 +14912,12 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB202_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB202_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -14926,10 +14926,10 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB202_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -14938,22 +14938,22 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB202_3
+; RV32IA-NEXT:    beq a1, s0, .LBB202_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB202_4
 ; RV32IA-NEXT:    j .LBB202_5
@@ -14970,12 +14970,12 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB202_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB202_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -14984,10 +14984,10 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB202_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -14996,24 +14996,24 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    blt s1, a2, .LBB202_3
+; RV64I-NEXT:    blt s0, a2, .LBB202_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB202_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB202_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB202_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15021,9 +15021,9 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB202_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -15041,22 +15041,22 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB203_3
+; RV32I-NEXT:    beq a1, s0, .LBB203_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB203_4
 ; RV32I-NEXT:    j .LBB203_5
@@ -15073,12 +15073,12 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB203_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB203_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -15087,10 +15087,10 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB203_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -15099,22 +15099,22 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB203_3
+; RV32IA-NEXT:    beq a1, s0, .LBB203_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB203_4
 ; RV32IA-NEXT:    j .LBB203_5
@@ -15131,12 +15131,12 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB203_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB203_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -15145,10 +15145,10 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB203_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -15157,24 +15157,24 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    blt s1, a2, .LBB203_3
+; RV64I-NEXT:    blt s0, a2, .LBB203_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB203_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15182,9 +15182,9 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB203_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -15202,22 +15202,22 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB204_3
+; RV32I-NEXT:    beq a1, s0, .LBB204_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB204_4
 ; RV32I-NEXT:    j .LBB204_5
@@ -15234,12 +15234,12 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB204_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB204_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -15248,10 +15248,10 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB204_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -15260,22 +15260,22 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB204_3
+; RV32IA-NEXT:    beq a1, s0, .LBB204_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB204_4
 ; RV32IA-NEXT:    j .LBB204_5
@@ -15292,12 +15292,12 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB204_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB204_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -15306,10 +15306,10 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB204_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -15318,24 +15318,24 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    blt s1, a2, .LBB204_3
+; RV64I-NEXT:    blt s0, a2, .LBB204_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB204_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB204_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB204_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15343,9 +15343,9 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB204_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -15363,22 +15363,22 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB205_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB205_3
+; RV32I-NEXT:    beq a1, s0, .LBB205_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB205_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    j .LBB205_4
 ; RV32I-NEXT:  .LBB205_3: # in Loop: Header=BB205_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -15396,12 +15396,12 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB205_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB205_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB205_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB205_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -15410,10 +15410,10 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB205_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -15422,22 +15422,22 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB205_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB205_3
+; RV32IA-NEXT:    beq a1, s0, .LBB205_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB205_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    j .LBB205_4
 ; RV32IA-NEXT:  .LBB205_3: # in Loop: Header=BB205_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -15455,12 +15455,12 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB205_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB205_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB205_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB205_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    mv a4, zero
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -15469,10 +15469,10 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB205_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -15481,24 +15481,24 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB205_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bge s1, a2, .LBB205_3
+; RV64I-NEXT:    bge s0, a2, .LBB205_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB205_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB205_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB205_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15506,9 +15506,9 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB205_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -15526,22 +15526,22 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB206_3
+; RV32I-NEXT:    beq a1, s0, .LBB206_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB206_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    j .LBB206_4
 ; RV32I-NEXT:  .LBB206_3: # in Loop: Header=BB206_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -15559,12 +15559,12 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB206_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB206_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB206_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB206_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -15573,10 +15573,10 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB206_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -15585,22 +15585,22 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB206_3
+; RV32IA-NEXT:    beq a1, s0, .LBB206_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB206_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    j .LBB206_4
 ; RV32IA-NEXT:  .LBB206_3: # in Loop: Header=BB206_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -15618,12 +15618,12 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB206_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB206_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB206_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB206_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 2
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -15632,10 +15632,10 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB206_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -15644,24 +15644,24 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bge s1, a2, .LBB206_3
+; RV64I-NEXT:    bge s0, a2, .LBB206_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB206_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB206_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB206_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15669,9 +15669,9 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB206_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -15689,22 +15689,22 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB207_3
+; RV32I-NEXT:    beq a1, s0, .LBB207_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB207_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    j .LBB207_4
 ; RV32I-NEXT:  .LBB207_3: # in Loop: Header=BB207_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -15722,12 +15722,12 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB207_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB207_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB207_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB207_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -15736,10 +15736,10 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB207_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -15748,22 +15748,22 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB207_3
+; RV32IA-NEXT:    beq a1, s0, .LBB207_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB207_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    j .LBB207_4
 ; RV32IA-NEXT:  .LBB207_3: # in Loop: Header=BB207_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -15781,12 +15781,12 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB207_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB207_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB207_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB207_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -15795,10 +15795,10 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB207_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -15807,24 +15807,24 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bge s1, a2, .LBB207_3
+; RV64I-NEXT:    bge s0, a2, .LBB207_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB207_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB207_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB207_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15832,9 +15832,9 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB207_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -15852,22 +15852,22 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB208_3
+; RV32I-NEXT:    beq a1, s0, .LBB208_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    j .LBB208_4
 ; RV32I-NEXT:  .LBB208_3: # in Loop: Header=BB208_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -15885,12 +15885,12 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB208_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB208_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -15899,10 +15899,10 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB208_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -15911,22 +15911,22 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB208_3
+; RV32IA-NEXT:    beq a1, s0, .LBB208_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    j .LBB208_4
 ; RV32IA-NEXT:  .LBB208_3: # in Loop: Header=BB208_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -15944,12 +15944,12 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB208_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB208_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -15958,10 +15958,10 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB208_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -15970,24 +15970,24 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bge s1, a2, .LBB208_3
+; RV64I-NEXT:    bge s0, a2, .LBB208_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB208_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -15995,9 +15995,9 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB208_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16015,22 +16015,22 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB209_3
+; RV32I-NEXT:    beq a1, s0, .LBB209_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB209_1 Depth=1
-; RV32I-NEXT:    slt a0, s1, a1
+; RV32I-NEXT:    slt a0, s0, a1
 ; RV32I-NEXT:    j .LBB209_4
 ; RV32I-NEXT:  .LBB209_3: # in Loop: Header=BB209_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -16048,12 +16048,12 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB209_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB209_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB209_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB209_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -16062,10 +16062,10 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB209_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -16074,22 +16074,22 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB209_3
+; RV32IA-NEXT:    beq a1, s0, .LBB209_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB209_1 Depth=1
-; RV32IA-NEXT:    slt a0, s1, a1
+; RV32IA-NEXT:    slt a0, s0, a1
 ; RV32IA-NEXT:    j .LBB209_4
 ; RV32IA-NEXT:  .LBB209_3: # in Loop: Header=BB209_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -16107,12 +16107,12 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB209_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB209_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB209_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB209_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -16121,10 +16121,10 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB209_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -16133,24 +16133,24 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bge s1, a2, .LBB209_3
+; RV64I-NEXT:    bge s0, a2, .LBB209_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB209_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB209_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB209_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -16158,9 +16158,9 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB209_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16178,22 +16178,22 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB210_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB210_3
+; RV32I-NEXT:    beq a1, s0, .LBB210_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB210_4
 ; RV32I-NEXT:    j .LBB210_5
@@ -16210,12 +16210,12 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB210_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB210_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -16224,10 +16224,10 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB210_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -16236,22 +16236,22 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB210_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB210_3
+; RV32IA-NEXT:    beq a1, s0, .LBB210_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB210_4
 ; RV32IA-NEXT:    j .LBB210_5
@@ -16268,12 +16268,12 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB210_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB210_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    mv a4, zero
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -16282,10 +16282,10 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB210_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -16294,24 +16294,24 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB210_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bltu s1, a2, .LBB210_3
+; RV64I-NEXT:    bltu s0, a2, .LBB210_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB210_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB210_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB210_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -16319,9 +16319,9 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB210_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16339,22 +16339,22 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB211_3
+; RV32I-NEXT:    beq a1, s0, .LBB211_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB211_4
 ; RV32I-NEXT:    j .LBB211_5
@@ -16371,12 +16371,12 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB211_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB211_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -16385,10 +16385,10 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB211_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -16397,22 +16397,22 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB211_3
+; RV32IA-NEXT:    beq a1, s0, .LBB211_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB211_4
 ; RV32IA-NEXT:    j .LBB211_5
@@ -16429,12 +16429,12 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB211_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB211_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 2
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -16443,10 +16443,10 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB211_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -16455,24 +16455,24 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bltu s1, a2, .LBB211_3
+; RV64I-NEXT:    bltu s0, a2, .LBB211_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB211_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB211_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB211_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -16480,9 +16480,9 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB211_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16500,22 +16500,22 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB212_3
+; RV32I-NEXT:    beq a1, s0, .LBB212_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB212_4
 ; RV32I-NEXT:    j .LBB212_5
@@ -16532,12 +16532,12 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB212_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB212_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -16546,10 +16546,10 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB212_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -16558,22 +16558,22 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB212_3
+; RV32IA-NEXT:    beq a1, s0, .LBB212_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB212_4
 ; RV32IA-NEXT:    j .LBB212_5
@@ -16590,12 +16590,12 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB212_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB212_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -16604,10 +16604,10 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB212_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -16616,24 +16616,24 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bltu s1, a2, .LBB212_3
+; RV64I-NEXT:    bltu s0, a2, .LBB212_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB212_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB212_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB212_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -16641,9 +16641,9 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB212_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16661,22 +16661,22 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB213_3
+; RV32I-NEXT:    beq a1, s0, .LBB213_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB213_4
 ; RV32I-NEXT:    j .LBB213_5
@@ -16693,12 +16693,12 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB213_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB213_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -16707,10 +16707,10 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB213_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -16719,22 +16719,22 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB213_3
+; RV32IA-NEXT:    beq a1, s0, .LBB213_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB213_4
 ; RV32IA-NEXT:    j .LBB213_5
@@ -16751,12 +16751,12 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB213_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB213_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -16765,10 +16765,10 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB213_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -16777,24 +16777,24 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bltu s1, a2, .LBB213_3
+; RV64I-NEXT:    bltu s0, a2, .LBB213_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB213_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -16802,9 +16802,9 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB213_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16822,22 +16822,22 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB214_3
+; RV32I-NEXT:    beq a1, s0, .LBB214_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB214_4
 ; RV32I-NEXT:    j .LBB214_5
@@ -16854,12 +16854,12 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB214_7
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB214_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -16868,10 +16868,10 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB214_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -16880,22 +16880,22 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB214_3
+; RV32IA-NEXT:    beq a1, s0, .LBB214_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB214_4
 ; RV32IA-NEXT:    j .LBB214_5
@@ -16912,12 +16912,12 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB214_7
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB214_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -16926,10 +16926,10 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB214_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -16938,24 +16938,24 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bltu s1, a2, .LBB214_3
+; RV64I-NEXT:    bltu s0, a2, .LBB214_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB214_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB214_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB214_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -16963,9 +16963,9 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB214_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -16983,22 +16983,22 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB215_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB215_3
+; RV32I-NEXT:    beq a1, s0, .LBB215_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB215_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    j .LBB215_4
 ; RV32I-NEXT:  .LBB215_3: # in Loop: Header=BB215_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -17016,12 +17016,12 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB215_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB215_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB215_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB215_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -17030,10 +17030,10 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB215_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -17042,22 +17042,22 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB215_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB215_3
+; RV32IA-NEXT:    beq a1, s0, .LBB215_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB215_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    j .LBB215_4
 ; RV32IA-NEXT:  .LBB215_3: # in Loop: Header=BB215_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -17075,12 +17075,12 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB215_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB215_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB215_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB215_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    mv a4, zero
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -17089,10 +17089,10 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB215_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -17101,24 +17101,24 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB215_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bgeu s1, a2, .LBB215_3
+; RV64I-NEXT:    bgeu s0, a2, .LBB215_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB215_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB215_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB215_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -17126,9 +17126,9 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB215_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -17146,22 +17146,22 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB216_3
+; RV32I-NEXT:    beq a1, s0, .LBB216_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB216_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    j .LBB216_4
 ; RV32I-NEXT:  .LBB216_3: # in Loop: Header=BB216_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -17179,12 +17179,12 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB216_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB216_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB216_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB216_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -17193,10 +17193,10 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB216_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -17205,22 +17205,22 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB216_3
+; RV32IA-NEXT:    beq a1, s0, .LBB216_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB216_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    j .LBB216_4
 ; RV32IA-NEXT:  .LBB216_3: # in Loop: Header=BB216_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -17238,12 +17238,12 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB216_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB216_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB216_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB216_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 2
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -17252,10 +17252,10 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB216_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -17264,24 +17264,24 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bgeu s1, a2, .LBB216_3
+; RV64I-NEXT:    bgeu s0, a2, .LBB216_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB216_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB216_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB216_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -17289,9 +17289,9 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB216_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -17309,22 +17309,22 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB217_3
+; RV32I-NEXT:    beq a1, s0, .LBB217_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB217_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    j .LBB217_4
 ; RV32I-NEXT:  .LBB217_3: # in Loop: Header=BB217_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -17342,12 +17342,12 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB217_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB217_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB217_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB217_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -17356,10 +17356,10 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB217_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -17368,22 +17368,22 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB217_3
+; RV32IA-NEXT:    beq a1, s0, .LBB217_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB217_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    j .LBB217_4
 ; RV32IA-NEXT:  .LBB217_3: # in Loop: Header=BB217_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -17401,12 +17401,12 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB217_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB217_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB217_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB217_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -17415,10 +17415,10 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB217_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -17427,24 +17427,24 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bgeu s1, a2, .LBB217_3
+; RV64I-NEXT:    bgeu s0, a2, .LBB217_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB217_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB217_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB217_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -17452,9 +17452,9 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB217_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -17472,22 +17472,22 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB218_3
+; RV32I-NEXT:    beq a1, s0, .LBB218_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    j .LBB218_4
 ; RV32I-NEXT:  .LBB218_3: # in Loop: Header=BB218_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -17505,12 +17505,12 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB218_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB218_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -17519,10 +17519,10 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB218_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -17531,22 +17531,22 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB218_3
+; RV32IA-NEXT:    beq a1, s0, .LBB218_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    j .LBB218_4
 ; RV32IA-NEXT:  .LBB218_3: # in Loop: Header=BB218_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -17564,12 +17564,12 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB218_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB218_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -17578,10 +17578,10 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB218_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -17590,24 +17590,24 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bgeu s1, a2, .LBB218_3
+; RV64I-NEXT:    bgeu s0, a2, .LBB218_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB218_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -17615,9 +17615,9 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB218_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
@@ -17635,22 +17635,22 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    mv s1, a2
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    mv s4, sp
+; RV32I-NEXT:    mv s3, sp
 ; RV32I-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a1, s1, .LBB219_3
+; RV32I-NEXT:    beq a1, s0, .LBB219_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB219_1 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a1
+; RV32I-NEXT:    sltu a0, s0, a1
 ; RV32I-NEXT:    j .LBB219_4
 ; RV32I-NEXT:  .LBB219_3: # in Loop: Header=BB219_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
@@ -17668,12 +17668,12 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB219_8
 ; RV32I-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB219_1 Depth=1
-; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:  .LBB219_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB219_1 Depth=1
 ; RV32I-NEXT:    sw a1, 4(sp)
-; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
@@ -17682,10 +17682,10 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB219_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -17694,22 +17694,22 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -32
 ; RV32IA-NEXT:    sw ra, 28(sp)
-; RV32IA-NEXT:    sw s1, 24(sp)
-; RV32IA-NEXT:    sw s2, 20(sp)
-; RV32IA-NEXT:    sw s3, 16(sp)
-; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    mv s1, a2
+; RV32IA-NEXT:    sw s0, 24(sp)
+; RV32IA-NEXT:    sw s1, 20(sp)
+; RV32IA-NEXT:    sw s2, 16(sp)
+; RV32IA-NEXT:    sw s3, 12(sp)
+; RV32IA-NEXT:    mv s0, a2
 ; RV32IA-NEXT:    mv s2, a1
-; RV32IA-NEXT:    mv s3, a0
+; RV32IA-NEXT:    mv s1, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    mv s4, sp
+; RV32IA-NEXT:    mv s3, sp
 ; RV32IA-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a1, s1, .LBB219_3
+; RV32IA-NEXT:    beq a1, s0, .LBB219_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB219_1 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a1
+; RV32IA-NEXT:    sltu a0, s0, a1
 ; RV32IA-NEXT:    j .LBB219_4
 ; RV32IA-NEXT:  .LBB219_3: # in Loop: Header=BB219_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
@@ -17727,12 +17727,12 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    bnez a0, .LBB219_8
 ; RV32IA-NEXT:  # %bb.7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB219_1 Depth=1
-; RV32IA-NEXT:    mv a3, s1
+; RV32IA-NEXT:    mv a3, s0
 ; RV32IA-NEXT:  .LBB219_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB219_1 Depth=1
 ; RV32IA-NEXT:    sw a1, 4(sp)
-; RV32IA-NEXT:    mv a0, s3
-; RV32IA-NEXT:    mv a1, s4
+; RV32IA-NEXT:    mv a0, s1
+; RV32IA-NEXT:    mv a1, s3
 ; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
@@ -17741,10 +17741,10 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB219_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s4, 12(sp)
-; RV32IA-NEXT:    lw s3, 16(sp)
-; RV32IA-NEXT:    lw s2, 20(sp)
-; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw s3, 12(sp)
+; RV32IA-NEXT:    lw s2, 16(sp)
+; RV32IA-NEXT:    lw s1, 20(sp)
+; RV32IA-NEXT:    lw s0, 24(sp)
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
@@ -17753,24 +17753,24 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
-; RV64I-NEXT:    sd s1, 32(sp)
-; RV64I-NEXT:    sd s2, 24(sp)
-; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    mv s1, a1
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    sd s0, 32(sp)
+; RV64I-NEXT:    sd s1, 24(sp)
+; RV64I-NEXT:    sd s2, 16(sp)
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s2, sp, 8
 ; RV64I-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
-; RV64I-NEXT:    bgeu s1, a2, .LBB219_3
+; RV64I-NEXT:    bgeu s0, a2, .LBB219_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB219_1 Depth=1
-; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:    mv a2, s0
 ; RV64I-NEXT:  .LBB219_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB219_1 Depth=1
-; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s2
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
@@ -17778,9 +17778,9 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    beqz a0, .LBB219_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s3, 16(sp)
-; RV64I-NEXT:    ld s2, 24(sp)
-; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld s2, 16(sp)
+; RV64I-NEXT:    ld s1, 24(sp)
+; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret

diff --git a/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index 532eedef6fbe80b038e753cb81a6e028830cda5c..0a29f24a277328c9d765a8000c30d4f36d468129 100644 (file)
--- a/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -257,13 +257,13 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
-; RV32I-NEXT:    sw s7, 0(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
+; RV32I-NEXT:    sw s5, 4(sp)
+; RV32I-NEXT:    sw s6, 0(sp)
 ; RV32I-NEXT:    mv s3, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    addi a0, a0, -1
@@ -275,18 +275,18 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
-; RV32I-NEXT:    addi s1, a1, 819
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    addi s0, a1, 819
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    and a0, a0, s0
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi s6, a1, 257
 ; RV32I-NEXT:    lui a1, 61681
-; RV32I-NEXT:    addi s7, a1, -241
-; RV32I-NEXT:    and a0, a0, s7
+; RV32I-NEXT:    addi s1, a1, -241
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
 ; RV32I-NEXT:    mv s2, a0
@@ -296,13 +296,13 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    and a0, a0, s0
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    and a0, a0, s7
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
 ; RV32I-NEXT:    bnez s4, .LBB7_2
@@ -314,13 +314,13 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV32I-NEXT:    srli a0, s2, 24
 ; RV32I-NEXT:  .LBB7_3:
 ; RV32I-NEXT:    mv a1, zero
-; RV32I-NEXT:    lw s7, 0(sp)
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s6, 0(sp)
+; RV32I-NEXT:    lw s5, 4(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
@@ -438,13 +438,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
-; RV32I-NEXT:    sw s1, 24(sp)
-; RV32I-NEXT:    sw s2, 20(sp)
-; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
-; RV32I-NEXT:    sw s7, 0(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    sw s1, 20(sp)
+; RV32I-NEXT:    sw s2, 16(sp)
+; RV32I-NEXT:    sw s3, 12(sp)
+; RV32I-NEXT:    sw s4, 8(sp)
+; RV32I-NEXT:    sw s5, 4(sp)
+; RV32I-NEXT:    sw s6, 0(sp)
 ; RV32I-NEXT:    mv s3, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    addi a0, a0, -1
@@ -456,18 +456,18 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
-; RV32I-NEXT:    addi s1, a1, 819
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    addi s0, a1, 819
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    and a0, a0, s0
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi s6, a1, 257
 ; RV32I-NEXT:    lui a1, 61681
-; RV32I-NEXT:    addi s7, a1, -241
-; RV32I-NEXT:    and a0, a0, s7
+; RV32I-NEXT:    addi s1, a1, -241
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
 ; RV32I-NEXT:    mv s2, a0
@@ -477,13 +477,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    and a1, a0, s1
+; RV32I-NEXT:    and a1, a0, s0
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:    and a0, a0, s0
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    and a0, a0, s7
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
 ; RV32I-NEXT:    bnez s4, .LBB11_2
@@ -495,13 +495,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV32I-NEXT:    srli a0, s2, 24
 ; RV32I-NEXT:  .LBB11_3:
 ; RV32I-NEXT:    mv a1, zero
-; RV32I-NEXT:    lw s7, 0(sp)
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
-; RV32I-NEXT:    lw s3, 16(sp)
-; RV32I-NEXT:    lw s2, 20(sp)
-; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw s6, 0(sp)
+; RV32I-NEXT:    lw s5, 4(sp)
+; RV32I-NEXT:    lw s4, 8(sp)
+; RV32I-NEXT:    lw s3, 12(sp)
+; RV32I-NEXT:    lw s2, 16(sp)
+; RV32I-NEXT:    lw s1, 20(sp)
+; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret

diff --git a/test/CodeGen/RISCV/callee-saved-gprs.ll b/test/CodeGen/RISCV/callee-saved-gprs.ll
index eb6844986dbb52315dc773afb476f01619debc15..e4c3fd5ebea1a427099a829ec21183562167202e 100644 (file)
--- a/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -9,23 +9,22 @@
 
 @var = global [32 x i32] zeroinitializer
 
-; TODO: s0 need not be reserved if the function doesn't use a framepointer.
-
 define void @foo() {
 ; RV32I-LABEL: foo:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -80
-; RV32I-NEXT:    sw s1, 76(sp)
-; RV32I-NEXT:    sw s2, 72(sp)
-; RV32I-NEXT:    sw s3, 68(sp)
-; RV32I-NEXT:    sw s4, 64(sp)
-; RV32I-NEXT:    sw s5, 60(sp)
-; RV32I-NEXT:    sw s6, 56(sp)
-; RV32I-NEXT:    sw s7, 52(sp)
-; RV32I-NEXT:    sw s8, 48(sp)
-; RV32I-NEXT:    sw s9, 44(sp)
-; RV32I-NEXT:    sw s10, 40(sp)
-; RV32I-NEXT:    sw s11, 36(sp)
+; RV32I-NEXT:    sw s0, 76(sp)
+; RV32I-NEXT:    sw s1, 72(sp)
+; RV32I-NEXT:    sw s2, 68(sp)
+; RV32I-NEXT:    sw s3, 64(sp)
+; RV32I-NEXT:    sw s4, 60(sp)
+; RV32I-NEXT:    sw s5, 56(sp)
+; RV32I-NEXT:    sw s6, 52(sp)
+; RV32I-NEXT:    sw s7, 48(sp)
+; RV32I-NEXT:    sw s8, 44(sp)
+; RV32I-NEXT:    sw s9, 40(sp)
+; RV32I-NEXT:    sw s10, 36(sp)
+; RV32I-NEXT:    sw s11, 32(sp)
 ; RV32I-NEXT:    lui a0, %hi(var)
 ; RV32I-NEXT:    addi a1, a0, %lo(var)
 ;
@@ -52,17 +51,18 @@ define void @foo() {
 ; RV64I-LABEL: foo:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -144
-; RV64I-NEXT:    sd s1, 136(sp)
-; RV64I-NEXT:    sd s2, 128(sp)
-; RV64I-NEXT:    sd s3, 120(sp)
-; RV64I-NEXT:    sd s4, 112(sp)
-; RV64I-NEXT:    sd s5, 104(sp)
-; RV64I-NEXT:    sd s6, 96(sp)
-; RV64I-NEXT:    sd s7, 88(sp)
-; RV64I-NEXT:    sd s8, 80(sp)
-; RV64I-NEXT:    sd s9, 72(sp)
-; RV64I-NEXT:    sd s10, 64(sp)
-; RV64I-NEXT:    sd s11, 56(sp)
+; RV64I-NEXT:    sd s0, 136(sp)
+; RV64I-NEXT:    sd s1, 128(sp)
+; RV64I-NEXT:    sd s2, 120(sp)
+; RV64I-NEXT:    sd s3, 112(sp)
+; RV64I-NEXT:    sd s4, 104(sp)
+; RV64I-NEXT:    sd s5, 96(sp)
+; RV64I-NEXT:    sd s6, 88(sp)
+; RV64I-NEXT:    sd s7, 80(sp)
+; RV64I-NEXT:    sd s8, 72(sp)
+; RV64I-NEXT:    sd s9, 64(sp)
+; RV64I-NEXT:    sd s10, 56(sp)
+; RV64I-NEXT:    sd s11, 48(sp)
 ; RV64I-NEXT:    lui a0, %hi(var)
 ; RV64I-NEXT:    addi a1, a0, %lo(var)
 ;

diff --git a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
index 5c1248aa5fd32bcfc4eeceeb0387b38af950bc30..f831cdae8ca73f888ad18e82a6f9c37ce6774129 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
+++ b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
@@ -16,13 +16,13 @@ define i32 @callee_double_in_regs(i32 %a, double %b) nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    sw s1, 8(sp)
-; RV32I-FPELIM-NEXT:    mv s1, a0
+; RV32I-FPELIM-NEXT:    sw s0, 8(sp)
+; RV32I-FPELIM-NEXT:    mv s0, a0
 ; RV32I-FPELIM-NEXT:    mv a0, a1
 ; RV32I-FPELIM-NEXT:    mv a1, a2
 ; RV32I-FPELIM-NEXT:    call __fixdfsi
-; RV32I-FPELIM-NEXT:    add a0, s1, a0
-; RV32I-FPELIM-NEXT:    lw s1, 8(sp)
+; RV32I-FPELIM-NEXT:    add a0, s0, a0
+; RV32I-FPELIM-NEXT:    lw s0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret

diff --git a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index 3d552220daf9e7d24bc547829014594f5b0e9bfe..f499ca8a0e94e54ba441cb0261df232b92964075 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -775,17 +775,17 @@ define i32 @caller_small_scalar_ret() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    sw s1, 8(sp)
+; RV32I-FPELIM-NEXT:    sw s0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 56
-; RV32I-FPELIM-NEXT:    addi s1, a0, 580
+; RV32I-FPELIM-NEXT:    addi s0, a0, 580
 ; RV32I-FPELIM-NEXT:    call callee_small_scalar_ret
-; RV32I-FPELIM-NEXT:    xor a1, a1, s1
+; RV32I-FPELIM-NEXT:    xor a1, a1, s0
 ; RV32I-FPELIM-NEXT:    lui a2, 200614
 ; RV32I-FPELIM-NEXT:    addi a2, a2, 647
 ; RV32I-FPELIM-NEXT:    xor a0, a0, a2
 ; RV32I-FPELIM-NEXT:    or a0, a0, a1
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
-; RV32I-FPELIM-NEXT:    lw s1, 8(sp)
+; RV32I-FPELIM-NEXT:    lw s0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret

diff --git a/test/CodeGen/RISCV/calling-conv-ilp32.ll b/test/CodeGen/RISCV/calling-conv-ilp32.ll
index 7bc51271866c8ca5d6008c178420964eaf31aee9..ddedab591d004191a3fb59d383e88a08b59ec179 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv-ilp32.ll
+++ b/test/CodeGen/RISCV/calling-conv-ilp32.ll
@@ -17,12 +17,12 @@ define i32 @callee_float_in_regs(i32 %a, float %b) nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    sw s1, 8(sp)
-; RV32I-FPELIM-NEXT:    mv s1, a0
+; RV32I-FPELIM-NEXT:    sw s0, 8(sp)
+; RV32I-FPELIM-NEXT:    mv s0, a0
 ; RV32I-FPELIM-NEXT:    mv a0, a1
 ; RV32I-FPELIM-NEXT:    call __fixsfsi
-; RV32I-FPELIM-NEXT:    add a0, s1, a0
-; RV32I-FPELIM-NEXT:    lw s1, 8(sp)
+; RV32I-FPELIM-NEXT:    add a0, s0, a0
+; RV32I-FPELIM-NEXT:    lw s0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret

diff --git a/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll b/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
index 5b1b3e96f3bba03de17298335fdaddf3d37ef174..205f57ff43788b332e00d885f324e703f7b54573 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
+++ b/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
@@ -11,12 +11,12 @@ define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    sd s1, 0(sp)
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    sd s0, 0(sp)
+; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    call __fixdfdi
-; RV64I-NEXT:    add a0, s1, a0
-; RV64I-NEXT:    ld s1, 0(sp)
+; RV64I-NEXT:    add a0, s0, a0
+; RV64I-NEXT:    ld s0, 0(sp)
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret

diff --git a/test/CodeGen/RISCV/calling-conv-lp64.ll b/test/CodeGen/RISCV/calling-conv-lp64.ll
index 8f8fbb4cc45db2195454bdce7192e1eef0c72992..faa68185a9f8887bdac948f78c2ee5972fdaeb65 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv-lp64.ll
+++ b/test/CodeGen/RISCV/calling-conv-lp64.ll
@@ -19,13 +19,13 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
 ; RV64I-FPELIM:       # %bb.0:
 ; RV64I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV64I-FPELIM-NEXT:    sd ra, 8(sp)
-; RV64I-FPELIM-NEXT:    sd s1, 0(sp)
-; RV64I-FPELIM-NEXT:    mv s1, a0
+; RV64I-FPELIM-NEXT:    sd s0, 0(sp)
+; RV64I-FPELIM-NEXT:    mv s0, a0
 ; RV64I-FPELIM-NEXT:    slli a0, a1, 32
 ; RV64I-FPELIM-NEXT:    srli a0, a0, 32
 ; RV64I-FPELIM-NEXT:    call __fixsfdi
-; RV64I-FPELIM-NEXT:    add a0, s1, a0
-; RV64I-FPELIM-NEXT:    ld s1, 0(sp)
+; RV64I-FPELIM-NEXT:    add a0, s0, a0
+; RV64I-FPELIM-NEXT:    ld s0, 0(sp)
 ; RV64I-FPELIM-NEXT:    ld ra, 8(sp)
 ; RV64I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV64I-FPELIM-NEXT:    ret

diff --git a/test/CodeGen/RISCV/calls.ll b/test/CodeGen/RISCV/calls.ll
index 4ef32fb7afb38301d5e38f25ccef25e5abfb0cd2..413b61d70b020c80c270da3808cb27eb1f4d74d0 100644 (file)
--- a/test/CodeGen/RISCV/calls.ll
+++ b/test/CodeGen/RISCV/calls.ll
@@ -71,11 +71,11 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s1, 8(sp)
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    sw s0, 8(sp)
+; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call fastcc_function
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    lw s1, 8(sp)
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -90,8 +90,8 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    sw s1, 8(sp)
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    sw s0, 8(sp)
+; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    sw a0, 4(sp)
 ; RV32I-NEXT:    sw a0, 0(sp)
 ; RV32I-NEXT:    mv a1, a0
@@ -102,8 +102,8 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
 ; RV32I-NEXT:    mv a6, a0
 ; RV32I-NEXT:    mv a7, a0
 ; RV32I-NEXT:    call external_many_args
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    lw s1, 8(sp)
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

diff --git a/test/CodeGen/RISCV/double-intrinsics.ll b/test/CodeGen/RISCV/double-intrinsics.ll
index 354601b91a8cecb486e3171d90a5d3cf63f1f662..29327452ff1257ee5083f5b0db7b22573a562d3c 100644 (file)
--- a/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/test/CodeGen/RISCV/double-intrinsics.ll
@@ -109,32 +109,32 @@ define double @sincos_f64(double %a) nounwind {
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    sw ra, 28(sp)
-; RV32IFD-NEXT:    sw s1, 24(sp)
-; RV32IFD-NEXT:    sw s2, 20(sp)
-; RV32IFD-NEXT:    sw s3, 16(sp)
-; RV32IFD-NEXT:    sw s4, 12(sp)
-; RV32IFD-NEXT:    mv s2, a1
+; RV32IFD-NEXT:    sw s0, 24(sp)
+; RV32IFD-NEXT:    sw s1, 20(sp)
+; RV32IFD-NEXT:    sw s2, 16(sp)
+; RV32IFD-NEXT:    sw s3, 12(sp)
+; RV32IFD-NEXT:    mv s0, a1
 ; RV32IFD-NEXT:    mv s1, a0
 ; RV32IFD-NEXT:    call sin
-; RV32IFD-NEXT:    mv s3, a0
-; RV32IFD-NEXT:    mv s4, a1
+; RV32IFD-NEXT:    mv s2, a0
+; RV32IFD-NEXT:    mv s3, a1
 ; RV32IFD-NEXT:    mv a0, s1
-; RV32IFD-NEXT:    mv a1, s2
+; RV32IFD-NEXT:    mv a1, s0
 ; RV32IFD-NEXT:    call cos
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a1, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
-; RV32IFD-NEXT:    sw s3, 0(sp)
-; RV32IFD-NEXT:    sw s4, 4(sp)
+; RV32IFD-NEXT:    sw s2, 0(sp)
+; RV32IFD-NEXT:    sw s3, 4(sp)
 ; RV32IFD-NEXT:    fld ft1, 0(sp)
 ; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV32IFD-NEXT:    fsd ft0, 0(sp)
 ; RV32IFD-NEXT:    lw a0, 0(sp)
 ; RV32IFD-NEXT:    lw a1, 4(sp)
-; RV32IFD-NEXT:    lw s4, 12(sp)
-; RV32IFD-NEXT:    lw s3, 16(sp)
-; RV32IFD-NEXT:    lw s2, 20(sp)
-; RV32IFD-NEXT:    lw s1, 24(sp)
+; RV32IFD-NEXT:    lw s3, 12(sp)
+; RV32IFD-NEXT:    lw s2, 16(sp)
+; RV32IFD-NEXT:    lw s1, 20(sp)
+; RV32IFD-NEXT:    lw s0, 24(sp)
 ; RV32IFD-NEXT:    lw ra, 28(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
@@ -143,19 +143,19 @@ define double @sincos_f64(double %a) nounwind {
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi sp, sp, -32
 ; RV64IFD-NEXT:    sd ra, 24(sp)
-; RV64IFD-NEXT:    sd s1, 16(sp)
-; RV64IFD-NEXT:    sd s2, 8(sp)
-; RV64IFD-NEXT:    mv s1, a0
+; RV64IFD-NEXT:    sd s0, 16(sp)
+; RV64IFD-NEXT:    sd s1, 8(sp)
+; RV64IFD-NEXT:    mv s0, a0
 ; RV64IFD-NEXT:    call sin
-; RV64IFD-NEXT:    mv s2, a0
-; RV64IFD-NEXT:    mv a0, s1
+; RV64IFD-NEXT:    mv s1, a0
+; RV64IFD-NEXT:    mv a0, s0
 ; RV64IFD-NEXT:    call cos
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
-; RV64IFD-NEXT:    fmv.d.x ft1, s2
+; RV64IFD-NEXT:    fmv.d.x ft1, s1
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
-; RV64IFD-NEXT:    ld s2, 8(sp)
-; RV64IFD-NEXT:    ld s1, 16(sp)
+; RV64IFD-NEXT:    ld s1, 8(sp)
+; RV64IFD-NEXT:    ld s0, 16(sp)
 ; RV64IFD-NEXT:    ld ra, 24(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 32
 ; RV64IFD-NEXT:    ret

diff --git a/test/CodeGen/RISCV/double-mem.ll b/test/CodeGen/RISCV/double-mem.ll
index a7a93de8a50e03af9219b1c55a2c5cae87c3edaa..76be198ff4d08d9ff0db17ee9eff8c9393aefef5 100644 (file)
--- a/test/CodeGen/RISCV/double-mem.ll
+++ b/test/CodeGen/RISCV/double-mem.ll
@@ -159,22 +159,22 @@ define double @fld_stack(double %a) nounwind {
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    sw ra, 28(sp)
-; RV32IFD-NEXT:    sw s1, 24(sp)
-; RV32IFD-NEXT:    sw s2, 20(sp)
-; RV32IFD-NEXT:    mv s2, a1
+; RV32IFD-NEXT:    sw s0, 24(sp)
+; RV32IFD-NEXT:    sw s1, 20(sp)
+; RV32IFD-NEXT:    mv s0, a1
 ; RV32IFD-NEXT:    mv s1, a0
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call notdead
 ; RV32IFD-NEXT:    sw s1, 0(sp)
-; RV32IFD-NEXT:    sw s2, 4(sp)
+; RV32IFD-NEXT:    sw s0, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV32IFD-NEXT:    fsd ft0, 0(sp)
 ; RV32IFD-NEXT:    lw a0, 0(sp)
 ; RV32IFD-NEXT:    lw a1, 4(sp)
-; RV32IFD-NEXT:    lw s2, 20(sp)
-; RV32IFD-NEXT:    lw s1, 24(sp)
+; RV32IFD-NEXT:    lw s1, 20(sp)
+; RV32IFD-NEXT:    lw s0, 24(sp)
 ; RV32IFD-NEXT:    lw ra, 28(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
@@ -183,15 +183,15 @@ define double @fld_stack(double %a) nounwind {
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi sp, sp, -32
 ; RV64IFD-NEXT:    sd ra, 24(sp)
-; RV64IFD-NEXT:    sd s1, 16(sp)
-; RV64IFD-NEXT:    mv s1, a0
+; RV64IFD-NEXT:    sd s0, 16(sp)
+; RV64IFD-NEXT:    mv s0, a0
 ; RV64IFD-NEXT:    addi a0, sp, 8
 ; RV64IFD-NEXT:    call notdead
-; RV64IFD-NEXT:    fmv.d.x ft0, s1
+; RV64IFD-NEXT:    fmv.d.x ft0, s0
 ; RV64IFD-NEXT:    fld ft1, 8(sp)
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
-; RV64IFD-NEXT:    ld s1, 16(sp)
+; RV64IFD-NEXT:    ld s0, 16(sp)
 ; RV64IFD-NEXT:    ld ra, 24(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 32
 ; RV64IFD-NEXT:    ret

diff --git a/test/CodeGen/RISCV/float-br-fcmp.ll b/test/CodeGen/RISCV/float-br-fcmp.ll
index 0e78c91bedf73fcec904ab8fcece08ca7a870dda..678d738d8ad248b2d06bcb12204efc4724bd80fe 100644 (file)
--- a/test/CodeGen/RISCV/float-br-fcmp.ll
+++ b/test/CodeGen/RISCV/float-br-fcmp.ll
@@ -754,20 +754,20 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -32
 ; RV64IF-NEXT:    sd ra, 24(sp)
-; RV64IF-NEXT:    sd s1, 16(sp)
+; RV64IF-NEXT:    sd s0, 16(sp)
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI17_0)
 ; RV64IF-NEXT:    addi a0, a0, %lo(.LCPI17_0)
 ; RV64IF-NEXT:    flw ft0, 0(a0)
 ; RV64IF-NEXT:    fsw ft0, 12(sp)
-; RV64IF-NEXT:    fmv.x.w s1, ft0
-; RV64IF-NEXT:    mv a0, s1
+; RV64IF-NEXT:    fmv.x.w s0, ft0
+; RV64IF-NEXT:    mv a0, s0
 ; RV64IF-NEXT:    call dummy
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    flw ft1, 12(sp)
 ; RV64IF-NEXT:    feq.s a0, ft0, ft1
 ; RV64IF-NEXT:    beqz a0, .LBB17_3
 ; RV64IF-NEXT:  # %bb.1: # %if.end
-; RV64IF-NEXT:    mv a0, s1
+; RV64IF-NEXT:    mv a0, s0
 ; RV64IF-NEXT:    call dummy
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    flw ft1, 12(sp)
@@ -775,7 +775,7 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    beqz a0, .LBB17_3
 ; RV64IF-NEXT:  # %bb.2: # %if.end4
 ; RV64IF-NEXT:    mv a0, zero
-; RV64IF-NEXT:    ld s1, 16(sp)
+; RV64IF-NEXT:    ld s0, 16(sp)
 ; RV64IF-NEXT:    ld ra, 24(sp)
 ; RV64IF-NEXT:    addi sp, sp, 32
 ; RV64IF-NEXT:    ret

diff --git a/test/CodeGen/RISCV/float-intrinsics.ll b/test/CodeGen/RISCV/float-intrinsics.ll
index 20248415468a0702223433a781d22b5126abb327..7ac2df6e89496d129c12318795cca6c54c8ee1a2 100644 (file)
--- a/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/test/CodeGen/RISCV/float-intrinsics.ll
@@ -107,19 +107,19 @@ define float @sincos_f32(float %a) nounwind {
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
-; RV32IF-NEXT:    sw s1, 8(sp)
-; RV32IF-NEXT:    sw s2, 4(sp)
-; RV32IF-NEXT:    mv s1, a0
+; RV32IF-NEXT:    sw s0, 8(sp)
+; RV32IF-NEXT:    sw s1, 4(sp)
+; RV32IF-NEXT:    mv s0, a0
 ; RV32IF-NEXT:    call sinf
-; RV32IF-NEXT:    mv s2, a0
-; RV32IF-NEXT:    mv a0, s1
+; RV32IF-NEXT:    mv s1, a0
+; RV32IF-NEXT:    mv a0, s0
 ; RV32IF-NEXT:    call cosf
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fmv.w.x ft1, s2
+; RV32IF-NEXT:    fmv.w.x ft1, s1
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
-; RV32IF-NEXT:    lw s2, 4(sp)
-; RV32IF-NEXT:    lw s1, 8(sp)
+; RV32IF-NEXT:    lw s1, 4(sp)
+; RV32IF-NEXT:    lw s0, 8(sp)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
@@ -128,19 +128,19 @@ define float @sincos_f32(float %a) nounwind {
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -32
 ; RV64IF-NEXT:    sd ra, 24(sp)
-; RV64IF-NEXT:    sd s1, 16(sp)
-; RV64IF-NEXT:    sd s2, 8(sp)
-; RV64IF-NEXT:    mv s1, a0
+; RV64IF-NEXT:    sd s0, 16(sp)
+; RV64IF-NEXT:    sd s1, 8(sp)
+; RV64IF-NEXT:    mv s0, a0
 ; RV64IF-NEXT:    call sinf
-; RV64IF-NEXT:    mv s2, a0
-; RV64IF-NEXT:    mv a0, s1
+; RV64IF-NEXT:    mv s1, a0
+; RV64IF-NEXT:    mv a0, s0
 ; RV64IF-NEXT:    call cosf
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fmv.w.x ft1, s2
+; RV64IF-NEXT:    fmv.w.x ft1, s1
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
-; RV64IF-NEXT:    ld s2, 8(sp)
-; RV64IF-NEXT:    ld s1, 16(sp)
+; RV64IF-NEXT:    ld s1, 8(sp)
+; RV64IF-NEXT:    ld s0, 16(sp)
 ; RV64IF-NEXT:    ld ra, 24(sp)
 ; RV64IF-NEXT:    addi sp, sp, 32
 ; RV64IF-NEXT:    ret

diff --git a/test/CodeGen/RISCV/float-mem.ll b/test/CodeGen/RISCV/float-mem.ll
index b90ee601b74a39f322cffbfaa03ea5873afc9723..2d1a7a7f9659452c65237c7cb47761f32bc99848 100644 (file)
--- a/test/CodeGen/RISCV/float-mem.ll
+++ b/test/CodeGen/RISCV/float-mem.ll
@@ -135,15 +135,15 @@ define float @flw_stack(float %a) nounwind {
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
-; RV32IF-NEXT:    sw s1, 8(sp)
-; RV32IF-NEXT:    mv s1, a0
+; RV32IF-NEXT:    sw s0, 8(sp)
+; RV32IF-NEXT:    mv s0, a0
 ; RV32IF-NEXT:    addi a0, sp, 4
 ; RV32IF-NEXT:    call notdead
-; RV32IF-NEXT:    fmv.w.x ft0, s1
+; RV32IF-NEXT:    fmv.w.x ft0, s0
 ; RV32IF-NEXT:    flw ft1, 4(sp)
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
-; RV32IF-NEXT:    lw s1, 8(sp)
+; RV32IF-NEXT:    lw s0, 8(sp)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
@@ -152,15 +152,15 @@ define float @flw_stack(float %a) nounwind {
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -32
 ; RV64IF-NEXT:    sd ra, 24(sp)
-; RV64IF-NEXT:    sd s1, 16(sp)
-; RV64IF-NEXT:    mv s1, a0
+; RV64IF-NEXT:    sd s0, 16(sp)
+; RV64IF-NEXT:    mv s0, a0
 ; RV64IF-NEXT:    addi a0, sp, 12
 ; RV64IF-NEXT:    call notdead
-; RV64IF-NEXT:    fmv.w.x ft0, s1
+; RV64IF-NEXT:    fmv.w.x ft0, s0
 ; RV64IF-NEXT:    flw ft1, 12(sp)
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
-; RV64IF-NEXT:    ld s1, 16(sp)
+; RV64IF-NEXT:    ld s0, 16(sp)
 ; RV64IF-NEXT:    ld ra, 24(sp)
 ; RV64IF-NEXT:    addi sp, sp, 32
 ; RV64IF-NEXT:    ret

diff --git a/test/CodeGen/RISCV/large-stack.ll b/test/CodeGen/RISCV/large-stack.ll
index 3e86871d457a59426217f5efcef34fc758193598..f414971223184796e5a59ac7f745e5e62bedcdb8 100644 (file)
--- a/test/CodeGen/RISCV/large-stack.ll
+++ b/test/CodeGen/RISCV/large-stack.ll
@@ -61,11 +61,11 @@ define void @test_emergency_spill_slot(i32 %a) nounwind {
 ; RV32I-FPELIM-NEXT:    lui a1, 98
 ; RV32I-FPELIM-NEXT:    addi a1, a1, -1396
 ; RV32I-FPELIM-NEXT:    add a1, sp, a1
-; RV32I-FPELIM-NEXT:    sw s1, 0(a1)
+; RV32I-FPELIM-NEXT:    sw s0, 0(a1)
 ; RV32I-FPELIM-NEXT:    lui a1, 98
 ; RV32I-FPELIM-NEXT:    addi a1, a1, -1400
 ; RV32I-FPELIM-NEXT:    add a1, sp, a1
-; RV32I-FPELIM-NEXT:    sw s2, 0(a1)
+; RV32I-FPELIM-NEXT:    sw s1, 0(a1)
 ; RV32I-FPELIM-NEXT:    lui a1, 78
 ; RV32I-FPELIM-NEXT:    addi a1, a1, 512
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 8
@@ -80,11 +80,11 @@ define void @test_emergency_spill_slot(i32 %a) nounwind {
 ; RV32I-FPELIM-NEXT:    lui a0, 98
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -1400
 ; RV32I-FPELIM-NEXT:    add a0, sp, a0
-; RV32I-FPELIM-NEXT:    lw s2, 0(a0)
+; RV32I-FPELIM-NEXT:    lw s1, 0(a0)
 ; RV32I-FPELIM-NEXT:    lui a0, 98
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -1396
 ; RV32I-FPELIM-NEXT:    add a0, sp, a0
-; RV32I-FPELIM-NEXT:    lw s1, 0(a0)
+; RV32I-FPELIM-NEXT:    lw s0, 0(a0)
 ; RV32I-FPELIM-NEXT:    lui a0, 98
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -1392
 ; RV32I-FPELIM-NEXT:    add sp, sp, a0

diff --git a/test/CodeGen/RISCV/remat.ll b/test/CodeGen/RISCV/remat.ll
index a1b8a6ce9e032c8a6a736e980fe43b76d0636480..2e9ad7a3f169ab6c8bbdc3fdf2e3910727942b29 100644 (file)
--- a/test/CodeGen/RISCV/remat.ll
+++ b/test/CodeGen/RISCV/remat.ll
@@ -23,19 +23,20 @@
 define i32 @test() nounwind {
 ; RV32I-LABEL: test:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
-; RV32I-NEXT:    sw s7, 16(sp)
-; RV32I-NEXT:    sw s8, 12(sp)
-; RV32I-NEXT:    sw s9, 8(sp)
-; RV32I-NEXT:    sw s10, 4(sp)
-; RV32I-NEXT:    sw s11, 0(sp)
+; RV32I-NEXT:    addi sp, sp, -64
+; RV32I-NEXT:    sw ra, 60(sp)
+; RV32I-NEXT:    sw s0, 56(sp)
+; RV32I-NEXT:    sw s1, 52(sp)
+; RV32I-NEXT:    sw s2, 48(sp)
+; RV32I-NEXT:    sw s3, 44(sp)
+; RV32I-NEXT:    sw s4, 40(sp)
+; RV32I-NEXT:    sw s5, 36(sp)
+; RV32I-NEXT:    sw s6, 32(sp)
+; RV32I-NEXT:    sw s7, 28(sp)
+; RV32I-NEXT:    sw s8, 24(sp)
+; RV32I-NEXT:    sw s9, 20(sp)
+; RV32I-NEXT:    sw s10, 16(sp)
+; RV32I-NEXT:    sw s11, 12(sp)
 ; RV32I-NEXT:    lui s9, %hi(a)
 ; RV32I-NEXT:    lw a0, %lo(a)(s9)
 ; RV32I-NEXT:    beqz a0, .LBB0_11
@@ -43,23 +44,24 @@ define i32 @test() nounwind {
 ; RV32I-NEXT:    lui s2, %hi(l)
 ; RV32I-NEXT:    lui s3, %hi(k)
 ; RV32I-NEXT:    lui s4, %hi(j)
-; RV32I-NEXT:    lui s5, %hi(i)
+; RV32I-NEXT:    lui s6, %hi(i)
+; RV32I-NEXT:    lui s5, %hi(h)
 ; RV32I-NEXT:    lui s7, %hi(g)
 ; RV32I-NEXT:    lui s8, %hi(f)
-; RV32I-NEXT:    lui s10, %hi(e)
-; RV32I-NEXT:    lui s1, %hi(d)
-; RV32I-NEXT:    lui s11, %hi(c)
-; RV32I-NEXT:    lui s6, %hi(b)
+; RV32I-NEXT:    lui s1, %hi(e)
+; RV32I-NEXT:    lui s0, %hi(d)
+; RV32I-NEXT:    lui s10, %hi(c)
+; RV32I-NEXT:    lui s11, %hi(b)
 ; RV32I-NEXT:  .LBB0_2: # %for.body
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    lw a1, %lo(l)(s2)
 ; RV32I-NEXT:    beqz a1, .LBB0_4
 ; RV32I-NEXT:  # %bb.3: # %if.then
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a4, %lo(e)(s10)
-; RV32I-NEXT:    lw a3, %lo(d)(s1)
-; RV32I-NEXT:    lw a2, %lo(c)(s11)
-; RV32I-NEXT:    lw a1, %lo(b)(s6)
+; RV32I-NEXT:    lw a4, %lo(e)(s1)
+; RV32I-NEXT:    lw a3, %lo(d)(s0)
+; RV32I-NEXT:    lw a2, %lo(c)(s10)
+; RV32I-NEXT:    lw a1, %lo(b)(s11)
 ; RV32I-NEXT:    addi a5, zero, 32
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_4: # %if.end
@@ -69,10 +71,10 @@ define i32 @test() nounwind {
 ; RV32I-NEXT:  # %bb.5: # %if.then3
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a4, %lo(f)(s8)
-; RV32I-NEXT:    lw a3, %lo(e)(s10)
-; RV32I-NEXT:    lw a2, %lo(d)(s1)
-; RV32I-NEXT:    lw a1, %lo(c)(s11)
-; RV32I-NEXT:    lw a0, %lo(b)(s6)
+; RV32I-NEXT:    lw a3, %lo(e)(s1)
+; RV32I-NEXT:    lw a2, %lo(d)(s0)
+; RV32I-NEXT:    lw a1, %lo(c)(s10)
+; RV32I-NEXT:    lw a0, %lo(b)(s11)
 ; RV32I-NEXT:    addi a5, zero, 64
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_6: # %if.end5
@@ -83,23 +85,22 @@ define i32 @test() nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a4, %lo(g)(s7)
 ; RV32I-NEXT:    lw a3, %lo(f)(s8)
-; RV32I-NEXT:    lw a2, %lo(e)(s10)
-; RV32I-NEXT:    lw a1, %lo(d)(s1)
-; RV32I-NEXT:    lw a0, %lo(c)(s11)
+; RV32I-NEXT:    lw a2, %lo(e)(s1)
+; RV32I-NEXT:    lw a1, %lo(d)(s0)
+; RV32I-NEXT:    lw a0, %lo(c)(s10)
 ; RV32I-NEXT:    addi a5, zero, 32
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_8: # %if.end9
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a0, %lo(i)(s5)
+; RV32I-NEXT:    lw a0, %lo(i)(s6)
 ; RV32I-NEXT:    beqz a0, .LBB0_10
 ; RV32I-NEXT:  # %bb.9: # %if.then11
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lui a0, %hi(h)
-; RV32I-NEXT:    lw a4, %lo(h)(a0)
+; RV32I-NEXT:    lw a4, %lo(h)(s5)
 ; RV32I-NEXT:    lw a3, %lo(g)(s7)
 ; RV32I-NEXT:    lw a2, %lo(f)(s8)
-; RV32I-NEXT:    lw a1, %lo(e)(s10)
-; RV32I-NEXT:    lw a0, %lo(d)(s1)
+; RV32I-NEXT:    lw a1, %lo(e)(s1)
+; RV32I-NEXT:    lw a0, %lo(d)(s0)
 ; RV32I-NEXT:    addi a5, zero, 32
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_10: # %for.inc
@@ -110,19 +111,20 @@ define i32 @test() nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB0_2
 ; RV32I-NEXT:  .LBB0_11: # %for.end
 ; RV32I-NEXT:    addi a0, zero, 1
-; RV32I-NEXT:    lw s11, 0(sp)
-; RV32I-NEXT:    lw s10, 4(sp)
-; RV32I-NEXT:    lw s9, 8(sp)
-; RV32I-NEXT:    lw s8, 12(sp)
-; RV32I-NEXT:    lw s7, 16(sp)
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s11, 12(sp)
+; RV32I-NEXT:    lw s10, 16(sp)
+; RV32I-NEXT:    lw s9, 20(sp)
+; RV32I-NEXT:    lw s8, 24(sp)
+; RV32I-NEXT:    lw s7, 28(sp)
+; RV32I-NEXT:    lw s6, 32(sp)
+; RV32I-NEXT:    lw s5, 36(sp)
+; RV32I-NEXT:    lw s4, 40(sp)
+; RV32I-NEXT:    lw s3, 44(sp)
+; RV32I-NEXT:    lw s2, 48(sp)
+; RV32I-NEXT:    lw s1, 52(sp)
+; RV32I-NEXT:    lw s0, 56(sp)
+; RV32I-NEXT:    lw ra, 60(sp)
+; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
 entry:
   %.pr = load i32, i32* @a, align 4

diff --git a/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll b/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
index 8d5b6dd56d7667bbe1a1c723ce280e37c51918b1..7bb4e28facba75a7892d170bc1180e4d22e1572e 100644 (file)
--- a/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
+++ b/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
@@ -16,12 +16,12 @@ define float @float_test(float %a, float %b) nounwind {
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
-; RV32IF-NEXT:    sw s1, 8(sp)
-; RV32IF-NEXT:    mv s1, a1
+; RV32IF-NEXT:    sw s0, 8(sp)
+; RV32IF-NEXT:    mv s0, a1
 ; RV32IF-NEXT:    call __addsf3
-; RV32IF-NEXT:    mv a1, s1
+; RV32IF-NEXT:    mv a1, s0
 ; RV32IF-NEXT:    call __divsf3
-; RV32IF-NEXT:    lw s1, 8(sp)
+; RV32IF-NEXT:    lw s0, 8(sp)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
@@ -30,16 +30,16 @@ define float @float_test(float %a, float %b) nounwind {
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp)
-; RV64IF-NEXT:    sd s1, 0(sp)
+; RV64IF-NEXT:    sd s0, 0(sp)
 ; RV64IF-NEXT:    slli a0, a0, 32
 ; RV64IF-NEXT:    srli a0, a0, 32
 ; RV64IF-NEXT:    slli a1, a1, 32
-; RV64IF-NEXT:    srli s1, a1, 32
-; RV64IF-NEXT:    mv a1, s1
+; RV64IF-NEXT:    srli s0, a1, 32
+; RV64IF-NEXT:    mv a1, s0
 ; RV64IF-NEXT:    call __addsf3
-; RV64IF-NEXT:    mv a1, s1
+; RV64IF-NEXT:    mv a1, s0
 ; RV64IF-NEXT:    call __divsf3
-; RV64IF-NEXT:    ld s1, 0(sp)
+; RV64IF-NEXT:    ld s0, 0(sp)
 ; RV64IF-NEXT:    ld ra, 8(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
@@ -53,16 +53,16 @@ define double @double_test(double %a, double %b) nounwind {
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
-; RV32IF-NEXT:    sw s1, 8(sp)
-; RV32IF-NEXT:    sw s2, 4(sp)
-; RV32IF-NEXT:    mv s2, a3
+; RV32IF-NEXT:    sw s0, 8(sp)
+; RV32IF-NEXT:    sw s1, 4(sp)
+; RV32IF-NEXT:    mv s0, a3
 ; RV32IF-NEXT:    mv s1, a2
 ; RV32IF-NEXT:    call __adddf3
 ; RV32IF-NEXT:    mv a2, s1
-; RV32IF-NEXT:    mv a3, s2
+; RV32IF-NEXT:    mv a3, s0
 ; RV32IF-NEXT:    call __divdf3
-; RV32IF-NEXT:    lw s2, 4(sp)
-; RV32IF-NEXT:    lw s1, 8(sp)
+; RV32IF-NEXT:    lw s1, 4(sp)
+; RV32IF-NEXT:    lw s0, 8(sp)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
@@ -71,12 +71,12 @@ define double @double_test(double %a, double %b) nounwind {
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp)
-; RV64IF-NEXT:    sd s1, 0(sp)
-; RV64IF-NEXT:    mv s1, a1
+; RV64IF-NEXT:    sd s0, 0(sp)
+; RV64IF-NEXT:    mv s0, a1
 ; RV64IF-NEXT:    call __adddf3
-; RV64IF-NEXT:    mv a1, s1
+; RV64IF-NEXT:    mv a1, s0
 ; RV64IF-NEXT:    call __divdf3
-; RV64IF-NEXT:    ld s1, 0(sp)
+; RV64IF-NEXT:    ld s0, 0(sp)
 ; RV64IF-NEXT:    ld ra, 8(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret

diff --git a/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll b/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
index ee3b507b976f0ee7019b587a1227eedc8c170d68..b45afb979fa0422c49e5315855d7981dd9dc169e 100644 (file)
--- a/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
+++ b/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
@@ -6,107 +6,107 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; RISCV32:       # %bb.0: # %start
 ; RISCV32-NEXT:    addi sp, sp, -80
 ; RISCV32-NEXT:    sw ra, 76(sp)
-; RISCV32-NEXT:    sw s1, 72(sp)
-; RISCV32-NEXT:    sw s2, 68(sp)
-; RISCV32-NEXT:    sw s3, 64(sp)
-; RISCV32-NEXT:    sw s4, 60(sp)
-; RISCV32-NEXT:    sw s5, 56(sp)
-; RISCV32-NEXT:    sw s6, 52(sp)
-; RISCV32-NEXT:    sw s7, 48(sp)
-; RISCV32-NEXT:    mv s3, a2
-; RISCV32-NEXT:    mv s1, a1
+; RISCV32-NEXT:    sw s0, 72(sp)
+; RISCV32-NEXT:    sw s1, 68(sp)
+; RISCV32-NEXT:    sw s2, 64(sp)
+; RISCV32-NEXT:    sw s3, 60(sp)
+; RISCV32-NEXT:    sw s4, 56(sp)
+; RISCV32-NEXT:    sw s5, 52(sp)
+; RISCV32-NEXT:    sw s6, 48(sp)
+; RISCV32-NEXT:    mv s1, a2
+; RISCV32-NEXT:    mv s0, a1
 ; RISCV32-NEXT:    mv s2, a0
 ; RISCV32-NEXT:    sw zero, 12(sp)
 ; RISCV32-NEXT:    sw zero, 8(sp)
 ; RISCV32-NEXT:    sw zero, 28(sp)
 ; RISCV32-NEXT:    sw zero, 24(sp)
-; RISCV32-NEXT:    lw s4, 4(a2)
-; RISCV32-NEXT:    sw s4, 4(sp)
-; RISCV32-NEXT:    lw s6, 0(a2)
-; RISCV32-NEXT:    sw s6, 0(sp)
-; RISCV32-NEXT:    lw s5, 4(a1)
-; RISCV32-NEXT:    sw s5, 20(sp)
-; RISCV32-NEXT:    lw s7, 0(a1)
-; RISCV32-NEXT:    sw s7, 16(sp)
+; RISCV32-NEXT:    lw s3, 4(a2)
+; RISCV32-NEXT:    sw s3, 4(sp)
+; RISCV32-NEXT:    lw s5, 0(a2)
+; RISCV32-NEXT:    sw s5, 0(sp)
+; RISCV32-NEXT:    lw s4, 4(a1)
+; RISCV32-NEXT:    sw s4, 20(sp)
+; RISCV32-NEXT:    lw s6, 0(a1)
+; RISCV32-NEXT:    sw s6, 16(sp)
 ; RISCV32-NEXT:    addi a0, sp, 32
 ; RISCV32-NEXT:    addi a1, sp, 16
 ; RISCV32-NEXT:    mv a2, sp
 ; RISCV32-NEXT:    call __multi3
-; RISCV32-NEXT:    lw t4, 12(s1)
-; RISCV32-NEXT:    lw a1, 8(s1)
-; RISCV32-NEXT:    mul a2, s4, a1
-; RISCV32-NEXT:    mul a3, t4, s6
-; RISCV32-NEXT:    add a7, a3, a2
-; RISCV32-NEXT:    lw a2, 12(s3)
-; RISCV32-NEXT:    lw a3, 8(s3)
-; RISCV32-NEXT:    mul a5, s5, a3
-; RISCV32-NEXT:    mul s1, a2, s7
+; RISCV32-NEXT:    lw a0, 12(s0)
+; RISCV32-NEXT:    lw a1, 8(s0)
+; RISCV32-NEXT:    mul a2, s3, a1
+; RISCV32-NEXT:    mul a3, a0, s5
+; RISCV32-NEXT:    add a4, a3, a2
+; RISCV32-NEXT:    lw a2, 12(s1)
+; RISCV32-NEXT:    lw a3, 8(s1)
+; RISCV32-NEXT:    mul a5, s4, a3
+; RISCV32-NEXT:    mul s1, a2, s6
 ; RISCV32-NEXT:    add a5, s1, a5
-; RISCV32-NEXT:    mul s1, a3, s7
-; RISCV32-NEXT:    mul a4, a1, s6
-; RISCV32-NEXT:    add s1, a4, s1
-; RISCV32-NEXT:    sltu a4, s1, a4
-; RISCV32-NEXT:    mulhu a6, a3, s7
+; RISCV32-NEXT:    mul s1, a3, s6
+; RISCV32-NEXT:    mul s0, a1, s5
+; RISCV32-NEXT:    add s1, s0, s1
+; RISCV32-NEXT:    sltu s0, s1, s0
+; RISCV32-NEXT:    mulhu a6, a3, s6
 ; RISCV32-NEXT:    add t1, a6, a5
-; RISCV32-NEXT:    mulhu t2, a1, s6
-; RISCV32-NEXT:    add t3, t2, a7
+; RISCV32-NEXT:    mulhu t2, a1, s5
+; RISCV32-NEXT:    add t3, t2, a4
 ; RISCV32-NEXT:    add a5, t3, t1
-; RISCV32-NEXT:    add a5, a5, a4
-; RISCV32-NEXT:    lw a4, 44(sp)
-; RISCV32-NEXT:    add a5, a4, a5
-; RISCV32-NEXT:    lw a0, 40(sp)
-; RISCV32-NEXT:    add a7, a0, s1
-; RISCV32-NEXT:    sltu t0, a7, a0
-; RISCV32-NEXT:    add s1, a5, t0
-; RISCV32-NEXT:    beq s1, a4, .LBB0_2
+; RISCV32-NEXT:    add a5, a5, s0
+; RISCV32-NEXT:    lw s0, 44(sp)
+; RISCV32-NEXT:    add a5, s0, a5
+; RISCV32-NEXT:    lw a4, 40(sp)
+; RISCV32-NEXT:    add a7, a4, s1
+; RISCV32-NEXT:    sltu t0, a7, a4
+; RISCV32-NEXT:    add a5, a5, t0
+; RISCV32-NEXT:    beq a5, s0, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1: # %start
-; RISCV32-NEXT:    sltu t0, s1, a4
+; RISCV32-NEXT:    sltu t0, a5, s0
 ; RISCV32-NEXT:  .LBB0_2: # %start
-; RISCV32-NEXT:    snez a0, s4
-; RISCV32-NEXT:    snez a4, t4
-; RISCV32-NEXT:    and a0, a4, a0
-; RISCV32-NEXT:    snez a4, s5
-; RISCV32-NEXT:    snez a5, a2
-; RISCV32-NEXT:    and a4, a5, a4
-; RISCV32-NEXT:    mulhu a5, a2, s7
-; RISCV32-NEXT:    snez a5, a5
-; RISCV32-NEXT:    or a4, a4, a5
-; RISCV32-NEXT:    mulhu a5, t4, s6
-; RISCV32-NEXT:    snez a5, a5
-; RISCV32-NEXT:    or a0, a0, a5
+; RISCV32-NEXT:    snez a4, s3
+; RISCV32-NEXT:    snez s1, a0
+; RISCV32-NEXT:    and a4, s1, a4
+; RISCV32-NEXT:    snez s1, s4
+; RISCV32-NEXT:    snez s0, a2
+; RISCV32-NEXT:    and s1, s0, s1
+; RISCV32-NEXT:    mulhu s0, a2, s6
+; RISCV32-NEXT:    snez s0, s0
+; RISCV32-NEXT:    or s1, s1, s0
+; RISCV32-NEXT:    mulhu s0, a0, s5
+; RISCV32-NEXT:    snez s0, s0
+; RISCV32-NEXT:    or a4, a4, s0
 ; RISCV32-NEXT:    sltu t2, t3, t2
-; RISCV32-NEXT:    mulhu a5, s4, a1
-; RISCV32-NEXT:    snez a5, a5
-; RISCV32-NEXT:    or t3, a0, a5
-; RISCV32-NEXT:    sltu a5, t1, a6
-; RISCV32-NEXT:    mulhu a0, s5, a3
-; RISCV32-NEXT:    snez a0, a0
-; RISCV32-NEXT:    or a0, a4, a0
-; RISCV32-NEXT:    lw a4, 36(sp)
-; RISCV32-NEXT:    sw a4, 4(s2)
-; RISCV32-NEXT:    lw a4, 32(sp)
-; RISCV32-NEXT:    sw a4, 0(s2)
+; RISCV32-NEXT:    mulhu s0, s3, a1
+; RISCV32-NEXT:    snez s0, s0
+; RISCV32-NEXT:    or t3, a4, s0
+; RISCV32-NEXT:    sltu s0, t1, a6
+; RISCV32-NEXT:    mulhu a4, s4, a3
+; RISCV32-NEXT:    snez a4, a4
+; RISCV32-NEXT:    or a4, s1, a4
+; RISCV32-NEXT:    lw s1, 36(sp)
+; RISCV32-NEXT:    sw s1, 4(s2)
+; RISCV32-NEXT:    lw s1, 32(sp)
+; RISCV32-NEXT:    sw s1, 0(s2)
 ; RISCV32-NEXT:    sw a7, 8(s2)
-; RISCV32-NEXT:    sw s1, 12(s2)
-; RISCV32-NEXT:    or a0, a0, a5
-; RISCV32-NEXT:    or a4, t3, t2
-; RISCV32-NEXT:    or a1, a1, t4
-; RISCV32-NEXT:    or a2, a3, a2
-; RISCV32-NEXT:    snez a2, a2
-; RISCV32-NEXT:    snez a1, a1
-; RISCV32-NEXT:    and a1, a1, a2
-; RISCV32-NEXT:    or a1, a1, a4
+; RISCV32-NEXT:    sw a5, 12(s2)
+; RISCV32-NEXT:    or a4, a4, s0
+; RISCV32-NEXT:    or a5, t3, t2
 ; RISCV32-NEXT:    or a0, a1, a0
+; RISCV32-NEXT:    or a1, a3, a2
+; RISCV32-NEXT:    snez a1, a1
+; RISCV32-NEXT:    snez a0, a0
+; RISCV32-NEXT:    and a0, a0, a1
+; RISCV32-NEXT:    or a0, a0, a5
+; RISCV32-NEXT:    or a0, a0, a4
 ; RISCV32-NEXT:    or a0, a0, t0
 ; RISCV32-NEXT:    andi a0, a0, 1
 ; RISCV32-NEXT:    sb a0, 16(s2)
-; RISCV32-NEXT:    lw s7, 48(sp)
-; RISCV32-NEXT:    lw s6, 52(sp)
-; RISCV32-NEXT:    lw s5, 56(sp)
-; RISCV32-NEXT:    lw s4, 60(sp)
-; RISCV32-NEXT:    lw s3, 64(sp)
-; RISCV32-NEXT:    lw s2, 68(sp)
-; RISCV32-NEXT:    lw s1, 72(sp)
+; RISCV32-NEXT:    lw s6, 48(sp)
+; RISCV32-NEXT:    lw s5, 52(sp)
+; RISCV32-NEXT:    lw s4, 56(sp)
+; RISCV32-NEXT:    lw s3, 60(sp)
+; RISCV32-NEXT:    lw s2, 64(sp)
+; RISCV32-NEXT:    lw s1, 68(sp)
+; RISCV32-NEXT:    lw s0, 72(sp)
 ; RISCV32-NEXT:    lw ra, 76(sp)
 ; RISCV32-NEXT:    addi sp, sp, 80
 ; RISCV32-NEXT:    ret

diff --git a/test/CodeGen/RISCV/vararg.ll b/test/CodeGen/RISCV/vararg.ll
index 60286a76e041c18be711d7a105c4e38bdf8c5bbe..3de0a230cc649ab1ff405358073e338fdfab31cf 100644 (file)
--- a/test/CodeGen/RISCV/vararg.ll
+++ b/test/CodeGen/RISCV/vararg.ll
@@ -534,8 +534,8 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -48
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    sw s1, 8(sp)
-; RV32I-FPELIM-NEXT:    mv s1, a1
+; RV32I-FPELIM-NEXT:    sw s0, 8(sp)
+; RV32I-FPELIM-NEXT:    mv s0, a1
 ; RV32I-FPELIM-NEXT:    sw a7, 44(sp)
 ; RV32I-FPELIM-NEXT:    sw a6, 40(sp)
 ; RV32I-FPELIM-NEXT:    sw a5, 36(sp)
@@ -562,11 +562,11 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
 ; RV32I-FPELIM-NEXT:    andi a0, a0, -4
 ; RV32I-FPELIM-NEXT:    addi a3, a0, 4
 ; RV32I-FPELIM-NEXT:    sw a3, 4(sp)
-; RV32I-FPELIM-NEXT:    add a1, a1, s1
+; RV32I-FPELIM-NEXT:    add a1, a1, s0
 ; RV32I-FPELIM-NEXT:    add a1, a1, a2
 ; RV32I-FPELIM-NEXT:    lw a0, 0(a0)
 ; RV32I-FPELIM-NEXT:    add a0, a1, a0
-; RV32I-FPELIM-NEXT:    lw s1, 8(sp)
+; RV32I-FPELIM-NEXT:    lw s0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32I-FPELIM-NEXT:    ret