[Pipeliner] Fix offset value for instrs dependent on post-inc load/stores

The software pipeliner and the packetizer try to break dependence
between the post-increment instruction and the dependent memory
instructions by changing the base register and the offset value.
However, in some cases, the existing logic didn't work properly
and created incorrect offset value.

Patch by Jyotsna Verma.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315468 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp
index 20141f7f8d60f905117c31e00260a4397dfee24e..c852c2e1564f93bbb2286ed9c0ac1e3e3a243e50 100644 (file)
--- a/lib/CodeGen/MachinePipeliner.cpp
+++ b/lib/CodeGen/MachinePipeliner.cpp
@@ -3892,9 +3892,14 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque<SUnit *> &Instrs) {
           unsigned BasePos, OffsetPos;
           // Update the base register and adjust the offset.
           if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) {
-            MI->getOperand(BasePos).setReg(NewBaseReg);
-            int64_t Offset = MI->getOperand(OffsetPos).getImm();
-            MI->getOperand(OffsetPos).setImm(Offset - It->second.second);
+            MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+            NewMI->getOperand(BasePos).setReg(NewBaseReg);
+            int64_t NewOffset =
+                MI->getOperand(OffsetPos).getImm() - It->second.second;
+            NewMI->getOperand(OffsetPos).setImm(NewOffset);
+            SU->setInstr(NewMI);
+            MISUnitMap[NewMI] = SU;
+            NewMIs.insert(NewMI);
           }
         }
         OverlapReg = 0;

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index c2125bec3a521ee898c57e363e23d974cf12433e..5e2cfbd531a19d442131a778c2b0987087a10217 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1651,13 +1651,14 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
       int &Value) const {
   if (isPostIncrement(MI)) {
-    // For a post-increment, the offset is zero and the increment value is
-    // determined by the instruction's access size.
-    int Zero;
-    unsigned AccessSize;
-    bool RetVal = getBaseAndOffset(MI, Zero, AccessSize);
-    Value = (int) AccessSize;
-    return RetVal;
+    unsigned BasePos = 0, OffsetPos = 0;
+    if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
+      return false;
+    const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
+    if (OffsetOp.isImm()) {
+      Value = OffsetOp.getImm();
+      return true;
+    }
   }
   if (MI.getOpcode() == Hexagon::A2_addi) {
     Value = MI.getOperand(2).getImm();