[ARM] GlobalISel: Legalize loading pointers

Make it legal to load pointer values. Also check that pointers are assigned
to the GPR reg bank by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293886 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index f12a4f70251783ea77a1fd40907fdb58f4a83927..d1276df57b189e5291638ea509b43e4fba3a319e 100644 (file)
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -35,7 +35,7 @@ ARMLegalizerInfo::ARMLegalizerInfo() {
 
   setAction({G_FRAME_INDEX, p0}, Legal);
 
-  for (auto Ty : {s1, s8, s16, s32})
+  for (auto Ty : {s1, s8, s16, s32, p0})
     setAction({G_LOAD, Ty}, Legal);
   setAction({G_LOAD, 1, p0}, Legal);
 

diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index d1e8ec3d18824d84c014fac81875cb335a5ad175..249a0b03795233acb5d90071a3e6f8241991c376 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -8,6 +8,7 @@
   define void @test_add_s32() { ret void }
 
   define void @test_load_from_stack() { ret void }
+  define void @test_legal_loads() { ret void }
 ...
 ---
 name:            test_sext_s8
@@ -156,3 +157,36 @@ body:             |
     %1(s32) = G_LOAD %0(p0)
     BX_RET 14, _
 ...
+---
+name:            test_legal_loads
+# CHECK-LABEL: name: test_legal_loads
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3
+
+    ; These are all legal, so we should find them unchanged in the output
+    ; CHECK-DAG: {{%[0-9]+}}(s32) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(s16) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(s8) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
+    %0(p0) = COPY %r0
+    %1(s32) = G_LOAD %0(p0)
+    %2(s16) = G_LOAD %0(p0)
+    %3(s8)  = G_LOAD %0(p0)
+    %4(s1)  = G_LOAD %0(p0)
+    %5(p0)  = G_LOAD %0(p0)
+    BX_RET 14, _
+...

diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index d520750ba309f7e0608f774a83d3348daf0f3e92..ba6880f3e43356102a73274b19693c0ff8b05361 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -123,6 +123,7 @@ selected:        false
 # CHECK: - { id: 2, class: gprb }
 # CHECK: - { id: 3, class: gprb }
 # CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
 
 registers:
   - { id: 0, class: _ }
@@ -130,6 +131,7 @@ registers:
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
+  - { id: 5, class: _ }
 body:             |
   bb.0:
     liveins: %r0
@@ -138,6 +140,7 @@ body:             |
     %2(s16) = G_LOAD %0
     %3(s8)  = G_LOAD %0
     %4(s1)  = G_LOAD %0
+    %5(p0)  = G_LOAD %0
     BX_RET 14, _, implicit %r0
 
 ...