]> granicus.if.org Git - llvm/commitdiff
[InlineSpiller] Only account for real spills in the hoisting logic
authorQuentin Colombet <qcolombet@apple.com>
Wed, 7 Jun 2017 00:22:07 +0000 (00:22 +0000)
committerQuentin Colombet <qcolombet@apple.com>
Wed, 7 Jun 2017 00:22:07 +0000 (00:22 +0000)
Spills of undef values shouldn't impact the placement of the relevant
spills. Drive by review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304850 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/InlineSpiller.cpp

index 68f2a2ed9a16b2dfa5688cfa8917286d5d1a1122..4e6a3ec218666b2bddb7dfaf4d9f049bfd44bbf7 100644 (file)
@@ -877,14 +877,16 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
   MachineBasicBlock &MBB = *MI->getParent();
 
   MachineInstrSpan MIS(MI);
-  if (isFullUndefDef(*MI))
+  bool IsRealSpill = true;
+  if (isFullUndefDef(*MI)) {
     // Don't spill undef value.
     // Anything works for undef, in particular keeping the memory
     // uninitialized is a viable option and it saves code size and
     // run time.
     BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
         .addReg(NewVReg, getKillRegState(isKill));
-  else
+    IsRealSpill = false;
+  } else
     TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
                             MRI.getRegClass(NewVReg), &TRI);
 
@@ -893,7 +895,8 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
   DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
                                            "spill"));
   ++NumSpills;
-  HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
+  if (IsRealSpill)
+    HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
 }
 
 /// spillAroundUses - insert spill code around each use of Reg.