Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

This reapplies commit r352010 with RISC-V test fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352237 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/RISCV/RISCVInstrInfo.cpp b/lib/Target/RISCV/RISCVInstrInfo.cpp
index d99d789fb7e9de106314296b0010e0eae1e3922c..afa872b4a5ce04205ff524f41a4394627fe2a505 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -447,3 +447,16 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   }
   }
 }
+
+bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
+  const unsigned Opcode = MI.getOpcode();
+  switch(Opcode) {
+    default:
+      break;
+    case RISCV::ADDI:
+    case RISCV::ORI:
+    case RISCV::XORI:
+      return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
+  }
+  return MI.isAsCheapAsAMove();
+}

diff --git a/lib/Target/RISCV/RISCVInstrInfo.h b/lib/Target/RISCV/RISCVInstrInfo.h
index 28a7e2fb2b6662ba3a129d379da6131bee5e090e..ff098e660d1915c52ddacd326460bb36f31b8a54 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/lib/Target/RISCV/RISCVInstrInfo.h
@@ -78,6 +78,8 @@ public:
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
+
+  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
 };
 }
 #endif

diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
index 7a874af9a916102d315029c7e887a0f4f02276b7..ab55ad2b1fae275a057aaf518a0b0ff275a597d9 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -315,7 +315,7 @@ class Priv<string opcodestr, bits<7> funct7>
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
                   "lui", "$rd, $imm20">;
 
@@ -351,13 +351,13 @@ def SW : Store_rri<0b010, "sw">;
 
 // ADDI isn't always rematerializable, but isReMaterializable will be used as
 // a hint which is verified in isReallyTriviallyReMaterializable.
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def ADDI  : ALU_ri<0b000, "addi">;
 
 def SLTI  : ALU_ri<0b010, "slti">;
 def SLTIU : ALU_ri<0b011, "sltiu">;
 
-let isReMaterializable = 1 in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 def XORI  : ALU_ri<0b100, "xori">;
 def ORI   : ALU_ri<0b110, "ori">;
 }

diff --git a/test/CodeGen/RISCV/atomic-cmpxchg.ll b/test/CodeGen/RISCV/atomic-cmpxchg.ll
index e31b45e8990e60089f0850ed51dce90c05a71981..c1113cdfb4d34dfbb341a5ef7bffc4b65589bf6f 100644 (file)
--- a/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -172,7 +172,7 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) {
 ; RV32I-NEXT:    sb a1, 11(sp)
 ; RV32I-NEXT:    addi a1, sp, 11
 ; RV32I-NEXT:    addi a3, zero, 2
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -209,7 +209,7 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) {
 ; RV64I-NEXT:    sb a1, 7(sp)
 ; RV64I-NEXT:    addi a1, sp, 7
 ; RV64I-NEXT:    addi a3, zero, 2
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -718,7 +718,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) {
 ; RV32I-NEXT:    sb a1, 11(sp)
 ; RV32I-NEXT:    addi a1, sp, 11
 ; RV32I-NEXT:    addi a3, zero, 5
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -755,7 +755,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) {
 ; RV64I-NEXT:    sb a1, 7(sp)
 ; RV64I-NEXT:    addi a1, sp, 7
 ; RV64I-NEXT:    addi a3, zero, 5
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -956,7 +956,7 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) {
 ; RV32I-NEXT:    sh a1, 10(sp)
 ; RV32I-NEXT:    addi a1, sp, 10
 ; RV32I-NEXT:    addi a3, zero, 2
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -994,7 +994,7 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) {
 ; RV64I-NEXT:    sh a1, 6(sp)
 ; RV64I-NEXT:    addi a1, sp, 6
 ; RV64I-NEXT:    addi a3, zero, 2
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -1516,7 +1516,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) {
 ; RV32I-NEXT:    sh a1, 10(sp)
 ; RV32I-NEXT:    addi a1, sp, 10
 ; RV32I-NEXT:    addi a3, zero, 5
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -1554,7 +1554,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) {
 ; RV64I-NEXT:    sh a1, 6(sp)
 ; RV64I-NEXT:    addi a1, sp, 6
 ; RV64I-NEXT:    addi a3, zero, 5
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -1700,7 +1700,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) {
 ; RV32I-NEXT:    sw a1, 8(sp)
 ; RV32I-NEXT:    addi a1, sp, 8
 ; RV32I-NEXT:    addi a3, zero, 2
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -1724,7 +1724,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) {
 ; RV64I-NEXT:    sw a1, 4(sp)
 ; RV64I-NEXT:    addi a1, sp, 4
 ; RV64I-NEXT:    addi a3, zero, 2
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -2064,7 +2064,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) {
 ; RV32I-NEXT:    sw a1, 8(sp)
 ; RV32I-NEXT:    addi a1, sp, 8
 ; RV32I-NEXT:    addi a3, zero, 5
-; RV32I-NEXT:    mv a4, a3
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -2088,7 +2088,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) {
 ; RV64I-NEXT:    sw a1, 4(sp)
 ; RV64I-NEXT:    addi a1, sp, 4
 ; RV64I-NEXT:    addi a3, zero, 5
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -2173,13 +2173,12 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a5, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
-; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a5
+; RV32I-NEXT:    mv a3, a4
+; RV32I-NEXT:    addi  a4, zero, 2
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -2190,13 +2189,12 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
-; RV32IA-NEXT:    addi a4, zero, 2
 ; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a5
+; RV32IA-NEXT:    mv a3, a4
+; RV32IA-NEXT:    addi a4, zero, 2
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
@@ -2238,10 +2236,10 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
-; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    mv a2, a3
 ; RV32I-NEXT:    mv a3, a4
-; RV32I-NEXT:    mv a4, a5
+; RV32I-NEXT:    addi a4, zero, 2
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -2254,10 +2252,10 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
-; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    mv a2, a3
 ; RV32IA-NEXT:    mv a3, a4
-; RV32IA-NEXT:    mv a4, a5
+; RV32IA-NEXT:    addi a4, zero, 2
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
@@ -2270,7 +2268,7 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV64I-NEXT:    sd a1, 0(sp)
 ; RV64I-NEXT:    mv a1, sp
 ; RV64I-NEXT:    addi a3, zero, 2
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -2295,13 +2293,12 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a5, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
-; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a5
+; RV32I-NEXT:    mv a3, a4
+; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -2312,13 +2309,12 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
-; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a5
+; RV32IA-NEXT:    mv a3, a4
+; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
@@ -2357,14 +2353,13 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a6, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
+; RV32I-NEXT:    mv a2, a3
+; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    addi a5, zero, 2
-; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a6
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -2374,14 +2369,13 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a6, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
+; RV32IA-NEXT:    mv a2, a3
+; RV32IA-NEXT:    mv a3, a4
 ; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    addi a5, zero, 2
-; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a6
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
@@ -2419,13 +2413,12 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a5, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
-; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a5
+; RV32I-NEXT:    mv a3, a4
+; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -2436,13 +2429,12 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
-; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a5
+; RV32IA-NEXT:    mv a3, a4
+; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
@@ -2481,14 +2473,13 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a6, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
+; RV32I-NEXT:    mv a2, a3
+; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    addi a4, zero, 4
 ; RV32I-NEXT:    addi a5, zero, 2
-; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a6
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -2498,14 +2489,13 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a6, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
+; RV32IA-NEXT:    mv a2, a3
+; RV32IA-NEXT:    mv a3, a4
 ; RV32IA-NEXT:    addi a4, zero, 4
 ; RV32IA-NEXT:    addi a5, zero, 2
-; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a6
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
@@ -2543,13 +2533,12 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a5, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
-; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a5
+; RV32I-NEXT:    mv a3, a4
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -2560,13 +2549,12 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
-; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a5
+; RV32IA-NEXT:    mv a3, a4
+; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
@@ -2605,14 +2593,13 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    mv a6, a4
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
+; RV32I-NEXT:    mv a2, a3
+; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    addi a5, zero, 2
-; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a3, a6
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -2622,14 +2609,13 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    addi sp, sp, -16
 ; RV32IA-NEXT:    sw ra, 12(sp)
-; RV32IA-NEXT:    mv a6, a4
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
+; RV32IA-NEXT:    mv a2, a3
+; RV32IA-NEXT:    mv a3, a4
 ; RV32IA-NEXT:    addi a4, zero, 5
 ; RV32IA-NEXT:    addi a5, zero, 2
-; RV32IA-NEXT:    mv a2, a3
-; RV32IA-NEXT:    mv a3, a6
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
@@ -2670,10 +2656,10 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32I-NEXT:    sw a2, 4(sp)
 ; RV32I-NEXT:    sw a1, 0(sp)
 ; RV32I-NEXT:    mv a1, sp
-; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    mv a2, a3
 ; RV32I-NEXT:    mv a3, a4
-; RV32I-NEXT:    mv a4, a5
+; RV32I-NEXT:    addi a4, zero, 5
+; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -2686,10 +2672,10 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV32IA-NEXT:    sw a2, 4(sp)
 ; RV32IA-NEXT:    sw a1, 0(sp)
 ; RV32IA-NEXT:    mv a1, sp
-; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    mv a2, a3
 ; RV32IA-NEXT:    mv a3, a4
-; RV32IA-NEXT:    mv a4, a5
+; RV32IA-NEXT:    addi a4, zero, 5
+; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
@@ -2702,7 +2688,7 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
 ; RV64I-NEXT:    sd a1, 0(sp)
 ; RV64I-NEXT:    mv a1, sp
 ; RV64I-NEXT:    addi a3, zero, 5
-; RV64I-NEXT:    mv a4, a3
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16

diff --git a/test/CodeGen/RISCV/atomic-rmw.ll b/test/CodeGen/RISCV/atomic-rmw.ll
index fa874e6fd2c565de4804014c004f1059845d0d11..9e98af6037c763e8104d4f2b6b7928f38ed8563c 100644 (file)
--- a/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/test/CodeGen/RISCV/atomic-rmw.ll
@@ -2227,36 +2227,33 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s5, a1, 24
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s5, a1, .LBB36_3
+; RV32I-NEXT:    blt s1, a1, .LBB36_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB36_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB36_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB36_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -2297,48 +2294,45 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s5, a1, 56
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s5, a1, .LBB36_3
+; RV64I-NEXT:    blt s1, a1, .LBB36_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB36_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB36_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_acquire:
@@ -2383,14 +2377,12 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
@@ -2402,17 +2394,16 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB37_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB37_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB37_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -2453,20 +2444,18 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
@@ -2478,23 +2467,22 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB37_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB37_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_release:
@@ -2539,16 +2527,12 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
-; RV32I-NEXT:    addi s3, sp, 3
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
@@ -2560,18 +2544,16 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB38_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB38_1 Depth=1
-; RV32I-NEXT:    sb a0, 3(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 3(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB38_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -2612,22 +2594,18 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
@@ -2640,23 +2618,21 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:  .LBB38_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB38_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
@@ -2701,36 +2677,33 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s5, a1, 24
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s5, a1, .LBB39_3
+; RV32I-NEXT:    blt s1, a1, .LBB39_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB39_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB39_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB39_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -2771,48 +2744,45 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s5, a1, 56
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s5, a1, .LBB39_3
+; RV64I-NEXT:    blt s1, a1, .LBB39_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB39_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB39_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
@@ -3007,36 +2977,33 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s5, a1, 24
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s5, a1, .LBB41_3
+; RV32I-NEXT:    bge s1, a1, .LBB41_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB41_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB41_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB41_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -3077,48 +3044,45 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s5, a1, 56
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s5, a1, .LBB41_3
+; RV64I-NEXT:    bge s1, a1, .LBB41_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB41_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB41_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_acquire:
@@ -3163,14 +3127,12 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
@@ -3182,17 +3144,16 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB42_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB42_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB42_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -3233,20 +3194,18 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
@@ -3258,23 +3217,22 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB42_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB42_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_release:
@@ -3319,16 +3277,12 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
-; RV32I-NEXT:    addi s3, sp, 3
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
@@ -3340,18 +3294,16 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB43_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB43_1 Depth=1
-; RV32I-NEXT:    sb a0, 3(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 3(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB43_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -3392,22 +3344,18 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
@@ -3420,23 +3368,21 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:  .LBB43_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB43_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
@@ -3481,36 +3427,33 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    srai s5, a1, 24
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    srai s1, a1, 24
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s5, a1, .LBB44_3
+; RV32I-NEXT:    bge s1, a1, .LBB44_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB44_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB44_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB44_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -3551,48 +3494,45 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
-; RV64I-NEXT:    srai s5, a1, 56
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s5, a1, .LBB44_3
+; RV64I-NEXT:    bge s1, a1, .LBB44_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB44_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB44_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
@@ -3773,34 +3713,31 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s5, a1, 255
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB46_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB46_3
+; RV32I-NEXT:    bltu s1, a1, .LBB46_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB46_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB46_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB46_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB46_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -3836,46 +3773,43 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s5, a1, 255
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB46_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB46_3
+; RV64I-NEXT:    bltu s1, a1, .LBB46_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB46_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB46_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB46_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB46_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
@@ -3915,13 +3849,11 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    andi s1, a1, 255
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB47_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
@@ -3932,17 +3864,16 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB47_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB47_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB47_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -3978,19 +3909,17 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    andi s1, a1, 255
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB47_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
@@ -4001,23 +3930,22 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB47_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB47_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB47_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i8_release:
@@ -4057,15 +3985,11 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    andi s1, a1, 255
-; RV32I-NEXT:    addi s3, sp, 3
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB48_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
@@ -4076,18 +4000,16 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB48_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB48_1 Depth=1
-; RV32I-NEXT:    sb a0, 3(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 3(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB48_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -4123,21 +4045,17 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    andi s1, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB48_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
@@ -4149,23 +4067,21 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:  .LBB48_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB48_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB48_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
@@ -4205,34 +4121,31 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s5, a1, 255
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s5, a1, .LBB49_3
+; RV32I-NEXT:    bltu s1, a1, .LBB49_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB49_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB49_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB49_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB49_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -4268,46 +4181,43 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s5, a1, 255
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB49_3
+; RV64I-NEXT:    bltu s1, a1, .LBB49_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB49_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB49_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB49_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB49_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
@@ -4483,34 +4393,31 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s5, a1, 255
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB51_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB51_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB51_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB51_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB51_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB51_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -4546,46 +4453,43 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s5, a1, 255
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB51_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB51_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB51_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB51_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB51_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB51_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
@@ -4625,13 +4529,11 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    andi s1, a1, 255
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
@@ -4642,17 +4544,16 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB52_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB52_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB52_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -4688,19 +4589,17 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    andi s1, a1, 255
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
@@ -4711,23 +4610,22 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB52_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB52_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB52_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i8_release:
@@ -4767,15 +4665,11 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    andi s1, a1, 255
-; RV32I-NEXT:    addi s3, sp, 3
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB53_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
@@ -4786,18 +4680,16 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB53_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB53_1 Depth=1
-; RV32I-NEXT:    sb a0, 3(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sb a0, 11(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 3(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB53_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -4833,21 +4725,17 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    andi s1, a1, 255
 ; RV64I-NEXT:    addi s3, sp, 7
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB53_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
@@ -4859,23 +4747,21 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV64I-NEXT:  .LBB53_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB53_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB53_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
@@ -4915,34 +4801,31 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
-; RV32I-NEXT:    andi s5, a1, 255
-; RV32I-NEXT:    addi s3, sp, 7
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    andi s1, a1, 255
+; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB54_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    andi a1, a0, 255
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s5, a1, .LBB54_3
+; RV32I-NEXT:    bgeu s1, a1, .LBB54_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB54_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB54_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB54_1 Depth=1
-; RV32I-NEXT:    sb a0, 7(sp)
+; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lb a0, 7(sp)
+; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB54_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -4978,46 +4861,43 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
-; RV64I-NEXT:    andi s5, a1, 255
-; RV64I-NEXT:    addi s3, sp, 15
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB54_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    andi a1, a0, 255
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB54_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB54_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB54_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB54_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB54_1 Depth=1
-; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB54_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
@@ -7359,36 +7239,33 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s5, a1, 16
-; RV32I-NEXT:    addi s3, sp, 6
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB91_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s5, a1, .LBB91_3
+; RV32I-NEXT:    blt s1, a1, .LBB91_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB91_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB91_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB91_1 Depth=1
-; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    sh a0, 10(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 6(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB91_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -7430,48 +7307,45 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s5, a1, 48
-; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB91_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s5, a1, .LBB91_3
+; RV64I-NEXT:    blt s1, a1, .LBB91_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB91_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB91_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB91_1 Depth=1
-; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    sh a0, 6(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB91_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i16_acquire:
@@ -7517,14 +7391,12 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    srai s1, a1, 16
-; RV32I-NEXT:    addi s3, sp, 6
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB92_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
@@ -7536,17 +7408,16 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB92_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB92_1 Depth=1
-; RV32I-NEXT:    sh a0, 6(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sh a0, 10(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 6(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB92_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -7588,20 +7459,18 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srai s1, a1, 48
-; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB92_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
@@ -7613,23 +7482,22 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB92_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB92_1 Depth=1
-; RV64I-NEXT:    sh a0, 14(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB92_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i16_release:
@@ -7675,16 +7543,12 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    srai s1, a1, 16
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB93_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
@@ -7696,18 +7560,16 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB93_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB93_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sh a0, 10(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB93_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -7749,22 +7611,18 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srai s1, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB93_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
@@ -7777,23 +7635,21 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:  .LBB93_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB93_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB93_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
@@ -7839,36 +7695,33 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s5, a1, 16
-; RV32I-NEXT:    addi s3, sp, 6
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB94_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    blt s5, a1, .LBB94_3
+; RV32I-NEXT:    blt s1, a1, .LBB94_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB94_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB94_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB94_1 Depth=1
-; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    sh a0, 10(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 6(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB94_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -7910,49 +7763,46 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s5, a1, 48
-; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB94_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s5, a1, .LBB94_3
+; RV64I-NEXT:    blt s1, a1, .LBB94_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB94_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB94_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB94_1 Depth=1
-; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    sh a0, 6(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB94_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    ret
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV64IA:       # %bb.0:
@@ -8149,36 +7999,33 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s5, a1, 16
-; RV32I-NEXT:    addi s3, sp, 6
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB96_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s5, a1, .LBB96_3
+; RV32I-NEXT:    bge s1, a1, .LBB96_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB96_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB96_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB96_1 Depth=1
-; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    sh a0, 10(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 6(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB96_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -8220,48 +8067,45 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s5, a1, 48
-; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB96_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s5, a1, .LBB96_3
+; RV64I-NEXT:    bge s1, a1, .LBB96_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB96_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB96_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB96_1 Depth=1
-; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    sh a0, 6(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB96_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i16_acquire:
@@ -8307,14 +8151,12 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    srai s1, a1, 16
-; RV32I-NEXT:    addi s3, sp, 6
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB97_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
@@ -8326,17 +8168,16 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB97_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB97_1 Depth=1
-; RV32I-NEXT:    sh a0, 6(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sh a0, 10(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 6(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB97_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -8378,20 +8219,18 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srai s1, a1, 48
-; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB97_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
@@ -8403,23 +8242,22 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB97_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB97_1 Depth=1
-; RV64I-NEXT:    sh a0, 14(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB97_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i16_release:
@@ -8465,16 +8303,12 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    srai s1, a1, 16
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB98_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
@@ -8486,18 +8320,16 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB98_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB98_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sh a0, 10(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB98_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -8539,22 +8371,18 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srai s1, a1, 48
 ; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB98_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
@@ -8567,23 +8395,21 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:  .LBB98_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB98_1 Depth=1
 ; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB98_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
@@ -8629,36 +8455,33 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 16
-; RV32I-NEXT:    srai s5, a1, 16
-; RV32I-NEXT:    addi s3, sp, 6
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    srai s1, a1, 16
+; RV32I-NEXT:    addi s3, sp, 10
 ; RV32I-NEXT:  .LBB99_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bge s5, a1, .LBB99_3
+; RV32I-NEXT:    bge s1, a1, .LBB99_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB99_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB99_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB99_1 Depth=1
-; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    sh a0, 10(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 6(sp)
+; RV32I-NEXT:    lh a0, 10(sp)
 ; RV32I-NEXT:    beqz a1, .LBB99_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -8700,48 +8523,45 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 48
-; RV64I-NEXT:    srai s5, a1, 48
-; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
 ; RV64I-NEXT:  .LBB99_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s5, a1, .LBB99_3
+; RV64I-NEXT:    bge s1, a1, .LBB99_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB99_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB99_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB99_1 Depth=1
-; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    sh a0, 6(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    lh a0, 6(sp)
 ; RV64I-NEXT:    beqz a1, .LBB99_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
@@ -8934,36 +8754,33 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s5, a1, -1
-; RV32I-NEXT:    and s6, s2, s5
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    addi s1, a1, -1
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB101_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s5
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s6, a1, .LBB101_3
+; RV32I-NEXT:    bltu s5, a1, .LBB101_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB101_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB101_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB101_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
+; RV32I-NEXT:    sh a0, 6(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB101_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
@@ -9008,36 +8825,33 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    sd s3, 32(sp)
 ; RV64I-NEXT:    sd s4, 24(sp)
 ; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s5, a1, -1
-; RV64I-NEXT:    and s6, s2, s5
-; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB101_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s6, a1, .LBB101_3
+; RV64I-NEXT:    bltu s5, a1, .LBB101_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB101_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB101_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB101_1 Depth=1
-; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    sh a0, 14(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB101_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    ld s5, 16(sp)
 ; RV64I-NEXT:    ld s4, 24(sp)
 ; RV64I-NEXT:    ld s3, 32(sp)
@@ -9086,36 +8900,33 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s6, s2, s1
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB102_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s6, a1, .LBB102_3
+; RV32I-NEXT:    bltu s5, a1, .LBB102_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB102_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB102_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB102_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB102_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
@@ -9160,36 +8971,33 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    sd s3, 32(sp)
 ; RV64I-NEXT:    sd s4, 24(sp)
 ; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s6, s2, s1
-; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB102_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s6, a1, .LBB102_3
+; RV64I-NEXT:    bltu s5, a1, .LBB102_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB102_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB102_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB102_1 Depth=1
-; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB102_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    ld s5, 16(sp)
 ; RV64I-NEXT:    ld s4, 24(sp)
 ; RV64I-NEXT:    ld s3, 32(sp)
@@ -9231,53 +9039,47 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
-; RV32I-NEXT:    sw s7, 16(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s7, s2, s1
-; RV32I-NEXT:    addi s3, sp, 14
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB103_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s7, a1, .LBB103_3
+; RV32I-NEXT:    bltu s5, a1, .LBB103_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB103_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB103_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB103_1 Depth=1
-; RV32I-NEXT:    sh a0, 14(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 14(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB103_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s7, 16(sp)
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s5, 8(sp)
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel:
@@ -9308,53 +9110,47 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -80
-; RV64I-NEXT:    sd ra, 72(sp)
-; RV64I-NEXT:    sd s1, 64(sp)
-; RV64I-NEXT:    sd s2, 56(sp)
-; RV64I-NEXT:    sd s3, 48(sp)
-; RV64I-NEXT:    sd s4, 40(sp)
-; RV64I-NEXT:    sd s5, 32(sp)
-; RV64I-NEXT:    sd s6, 24(sp)
-; RV64I-NEXT:    sd s7, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s7, s2, s1
+; RV64I-NEXT:    and s5, s2, s1
 ; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB103_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s7, a1, .LBB103_3
+; RV64I-NEXT:    bltu s5, a1, .LBB103_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB103_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB103_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB103_1 Depth=1
 ; RV64I-NEXT:    sh a0, 14(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB103_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s7, 16(sp)
-; RV64I-NEXT:    ld s6, 24(sp)
-; RV64I-NEXT:    ld s5, 32(sp)
-; RV64I-NEXT:    ld s4, 40(sp)
-; RV64I-NEXT:    ld s3, 48(sp)
-; RV64I-NEXT:    ld s2, 56(sp)
-; RV64I-NEXT:    ld s1, 64(sp)
-; RV64I-NEXT:    ld ra, 72(sp)
-; RV64I-NEXT:    addi sp, sp, 80
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
@@ -9396,36 +9192,33 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s5, a1, -1
-; RV32I-NEXT:    and s6, s2, s5
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    addi s1, a1, -1
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB104_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s5
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bltu s6, a1, .LBB104_3
+; RV32I-NEXT:    bltu s5, a1, .LBB104_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB104_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB104_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB104_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
+; RV32I-NEXT:    sh a0, 6(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB104_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
@@ -9470,36 +9263,33 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    sd s3, 32(sp)
 ; RV64I-NEXT:    sd s4, 24(sp)
 ; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s5, a1, -1
-; RV64I-NEXT:    and s6, s2, s5
-; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB104_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s6, a1, .LBB104_3
+; RV64I-NEXT:    bltu s5, a1, .LBB104_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB104_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB104_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB104_1 Depth=1
-; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    sh a0, 14(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB104_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    ld s5, 16(sp)
 ; RV64I-NEXT:    ld s4, 24(sp)
 ; RV64I-NEXT:    ld s3, 32(sp)
@@ -9694,36 +9484,33 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s5, a1, -1
-; RV32I-NEXT:    and s6, s2, s5
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s1, zero, 2
+; RV32I-NEXT:    addi s1, a1, -1
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB106_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s5
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s6, a1, .LBB106_3
+; RV32I-NEXT:    bgeu s5, a1, .LBB106_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB106_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB106_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB106_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
+; RV32I-NEXT:    sh a0, 6(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB106_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
@@ -9768,36 +9555,33 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    sd s3, 32(sp)
 ; RV64I-NEXT:    sd s4, 24(sp)
 ; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s5, a1, -1
-; RV64I-NEXT:    and s6, s2, s5
-; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB106_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s6, a1, .LBB106_3
+; RV64I-NEXT:    bgeu s5, a1, .LBB106_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB106_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB106_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB106_1 Depth=1
-; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    sh a0, 14(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB106_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    ld s5, 16(sp)
 ; RV64I-NEXT:    ld s4, 24(sp)
 ; RV64I-NEXT:    ld s3, 32(sp)
@@ -9846,36 +9630,33 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s6, s2, s1
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB107_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s6, a1, .LBB107_3
+; RV32I-NEXT:    bgeu s5, a1, .LBB107_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB107_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB107_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB107_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
-; RV32I-NEXT:    mv a0, s5
+; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB107_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
@@ -9920,36 +9701,33 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    sd s3, 32(sp)
 ; RV64I-NEXT:    sd s4, 24(sp)
 ; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s6, s2, s1
-; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB107_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s6, a1, .LBB107_3
+; RV64I-NEXT:    bgeu s5, a1, .LBB107_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB107_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB107_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB107_1 Depth=1
-; RV64I-NEXT:    sh a0, 6(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB107_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    ld s5, 16(sp)
 ; RV64I-NEXT:    ld s4, 24(sp)
 ; RV64I-NEXT:    ld s3, 32(sp)
@@ -9991,53 +9769,47 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
-; RV32I-NEXT:    sw s7, 16(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi s1, a1, -1
-; RV32I-NEXT:    and s7, s2, s1
-; RV32I-NEXT:    addi s3, sp, 14
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB108_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s7, a1, .LBB108_3
+; RV32I-NEXT:    bgeu s5, a1, .LBB108_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB108_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB108_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB108_1 Depth=1
-; RV32I-NEXT:    sh a0, 14(sp)
-; RV32I-NEXT:    mv a0, s6
+; RV32I-NEXT:    sh a0, 6(sp)
+; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 14(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB108_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s7, 16(sp)
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s5, 8(sp)
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel:
@@ -10068,53 +9840,47 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -80
-; RV64I-NEXT:    sd ra, 72(sp)
-; RV64I-NEXT:    sd s1, 64(sp)
-; RV64I-NEXT:    sd s2, 56(sp)
-; RV64I-NEXT:    sd s3, 48(sp)
-; RV64I-NEXT:    sd s4, 40(sp)
-; RV64I-NEXT:    sd s5, 32(sp)
-; RV64I-NEXT:    sd s6, 24(sp)
-; RV64I-NEXT:    sd s7, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw s1, a1, -1
-; RV64I-NEXT:    and s7, s2, s1
+; RV64I-NEXT:    and s5, s2, s1
 ; RV64I-NEXT:    addi s3, sp, 14
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB108_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s7, a1, .LBB108_3
+; RV64I-NEXT:    bgeu s5, a1, .LBB108_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB108_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB108_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB108_1 Depth=1
 ; RV64I-NEXT:    sh a0, 14(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB108_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s7, 16(sp)
-; RV64I-NEXT:    ld s6, 24(sp)
-; RV64I-NEXT:    ld s5, 32(sp)
-; RV64I-NEXT:    ld s4, 40(sp)
-; RV64I-NEXT:    ld s3, 48(sp)
-; RV64I-NEXT:    ld s2, 56(sp)
-; RV64I-NEXT:    ld s1, 64(sp)
-; RV64I-NEXT:    ld ra, 72(sp)
-; RV64I-NEXT:    addi sp, sp, 80
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
@@ -10156,36 +9922,33 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
-; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lhu a0, 0(a0)
 ; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi s5, a1, -1
-; RV32I-NEXT:    and s6, s2, s5
-; RV32I-NEXT:    addi s3, sp, 2
-; RV32I-NEXT:    addi s1, zero, 5
+; RV32I-NEXT:    addi s1, a1, -1
+; RV32I-NEXT:    and s5, s2, s1
+; RV32I-NEXT:    addi s3, sp, 6
 ; RV32I-NEXT:  .LBB109_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    and a1, a0, s5
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    bgeu s6, a1, .LBB109_3
+; RV32I-NEXT:    bgeu s5, a1, .LBB109_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB109_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB109_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB109_1 Depth=1
-; RV32I-NEXT:    sh a0, 2(sp)
+; RV32I-NEXT:    sh a0, 6(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_2
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    lh a0, 2(sp)
+; RV32I-NEXT:    lh a0, 6(sp)
 ; RV32I-NEXT:    beqz a1, .LBB109_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
@@ -10230,36 +9993,33 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV64I-NEXT:    sd s3, 32(sp)
 ; RV64I-NEXT:    sd s4, 24(sp)
 ; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lhu a0, 0(a0)
 ; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw s5, a1, -1
-; RV64I-NEXT:    and s6, s2, s5
-; RV64I-NEXT:    addi s3, sp, 6
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
 ; RV64I-NEXT:  .LBB109_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    and a1, a0, s1
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s6, a1, .LBB109_3
+; RV64I-NEXT:    bgeu s5, a1, .LBB109_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB109_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB109_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB109_1 Depth=1
-; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    sh a0, 14(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_2
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    lh a0, 14(sp)
 ; RV64I-NEXT:    beqz a1, .LBB109_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    ld s5, 16(sp)
 ; RV64I-NEXT:    ld s4, 24(sp)
 ; RV64I-NEXT:    ld s3, 32(sp)
@@ -11667,15 +11427,13 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB146_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    blt s1, a2, .LBB146_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB146_1 Depth=1
@@ -11684,14 +11442,13 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB146_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB146_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -11706,46 +11463,43 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i32_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB146_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s5, a1, .LBB146_3
+; RV64I-NEXT:    blt s1, a1, .LBB146_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB146_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB146_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB146_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB146_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i32_acquire:
@@ -11764,15 +11518,13 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB147_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    blt s1, a2, .LBB147_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB147_1 Depth=1
@@ -11781,14 +11533,13 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB147_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB147_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -11803,19 +11554,17 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i32_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB147_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -11826,23 +11575,22 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB147_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB147_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB147_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i32_release:
@@ -11861,17 +11609,13 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 4
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB148_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 4(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    blt s1, a2, .LBB148_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB148_1 Depth=1
@@ -11880,15 +11624,13 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB148_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 4(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB148_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -11903,21 +11645,17 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
 ; RV64I-NEXT:    addi s3, sp, 4
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB148_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -11929,23 +11667,21 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:  .LBB148_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB148_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB148_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i32_acq_rel:
@@ -11964,15 +11700,13 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 5
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB149_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    blt s1, a2, .LBB149_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB149_1 Depth=1
@@ -11981,14 +11715,13 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB149_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB149_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12003,46 +11736,43 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB149_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    blt s5, a1, .LBB149_3
+; RV64I-NEXT:    blt s1, a1, .LBB149_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB149_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB149_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB149_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB149_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
@@ -12152,15 +11882,13 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB151_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bge s1, a2, .LBB151_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB151_1 Depth=1
@@ -12169,14 +11897,13 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB151_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB151_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12191,46 +11918,43 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i32_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB151_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s5, a1, .LBB151_3
+; RV64I-NEXT:    bge s1, a1, .LBB151_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB151_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB151_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB151_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB151_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i32_acquire:
@@ -12249,15 +11973,13 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB152_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bge s1, a2, .LBB152_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB152_1 Depth=1
@@ -12266,14 +11988,13 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB152_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB152_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12288,19 +12009,17 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i32_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB152_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -12311,23 +12030,22 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB152_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB152_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB152_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i32_release:
@@ -12346,17 +12064,13 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 4
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB153_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 4(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bge s1, a2, .LBB153_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB153_1 Depth=1
@@ -12365,15 +12079,13 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB153_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 4(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB153_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12388,21 +12100,17 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
 ; RV64I-NEXT:    addi s3, sp, 4
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB153_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -12414,23 +12122,21 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:  .LBB153_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB153_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB153_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i32_acq_rel:
@@ -12449,15 +12155,13 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 5
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB154_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bge s1, a2, .LBB154_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB154_1 Depth=1
@@ -12466,14 +12170,13 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB154_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB154_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12488,46 +12191,43 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB154_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bge s5, a1, .LBB154_3
+; RV64I-NEXT:    bge s1, a1, .LBB154_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB154_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB154_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB154_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB154_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
@@ -12637,15 +12337,13 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB156_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bltu s1, a2, .LBB156_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB156_1 Depth=1
@@ -12654,14 +12352,13 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB156_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB156_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12676,46 +12373,43 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i32_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB156_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB156_3
+; RV64I-NEXT:    bltu s1, a1, .LBB156_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB156_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB156_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB156_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB156_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i32_acquire:
@@ -12734,15 +12428,13 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB157_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bltu s1, a2, .LBB157_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB157_1 Depth=1
@@ -12751,14 +12443,13 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB157_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB157_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12773,19 +12464,17 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i32_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB157_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -12796,23 +12485,22 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB157_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB157_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB157_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i32_release:
@@ -12831,17 +12519,13 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 4
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB158_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 4(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bltu s1, a2, .LBB158_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB158_1 Depth=1
@@ -12850,15 +12534,13 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB158_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 4(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB158_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12873,21 +12555,17 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
 ; RV64I-NEXT:    addi s3, sp, 4
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB158_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -12899,23 +12577,21 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:  .LBB158_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB158_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB158_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel:
@@ -12934,15 +12610,13 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 5
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB159_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bltu s1, a2, .LBB159_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB159_1 Depth=1
@@ -12951,14 +12625,13 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB159_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB159_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -12973,46 +12646,43 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB159_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bltu s5, a1, .LBB159_3
+; RV64I-NEXT:    bltu s1, a1, .LBB159_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB159_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB159_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB159_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB159_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
@@ -13122,15 +12792,13 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB161_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bgeu s1, a2, .LBB161_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB161_1 Depth=1
@@ -13139,14 +12807,13 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB161_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 2
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB161_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -13161,46 +12828,43 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i32_acquire:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB161_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB161_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB161_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB161_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB161_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB161_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB161_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i32_acquire:
@@ -13219,15 +12883,13 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 3
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB162_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bgeu s1, a2, .LBB162_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB162_1 Depth=1
@@ -13236,14 +12898,13 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB162_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB162_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -13258,19 +12919,17 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i32_release:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB162_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -13281,23 +12940,22 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB162_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB162_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
-; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB162_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i32_release:
@@ -13316,17 +12974,13 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 4
-; RV32I-NEXT:    addi s4, zero, 4
-; RV32I-NEXT:    addi s5, zero, 2
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB163_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 4(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bgeu s1, a2, .LBB163_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB163_1 Depth=1
@@ -13335,15 +12989,13 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB163_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a3, zero, 4
+; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 4(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB163_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -13358,21 +13010,17 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
-; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
-; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
 ; RV64I-NEXT:    sext.w s1, a1
 ; RV64I-NEXT:    addi s3, sp, 4
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB163_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
@@ -13384,23 +13032,21 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
 ; RV64I-NEXT:  .LBB163_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB163_1 Depth=1
 ; RV64I-NEXT:    sw a0, 4(sp)
-; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB163_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s6, 8(sp)
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel:
@@ -13419,15 +13065,13 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
-; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s3, sp, 8
-; RV32I-NEXT:    addi s4, zero, 5
+; RV32I-NEXT:    addi s3, sp, 12
 ; RV32I-NEXT:  .LBB164_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 12(sp)
 ; RV32I-NEXT:    bgeu s1, a2, .LBB164_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB164_1 Depth=1
@@ -13436,14 +13080,13 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-NEXT:    # in Loop: Header=BB164_1 Depth=1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    mv a3, s4
-; RV32I-NEXT:    mv a4, s4
+; RV32I-NEXT:    addi a3, zero, 5
+; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a2, 12(sp)
 ; RV32I-NEXT:    beqz a0, .LBB164_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
@@ -13458,46 +13101,43 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ;
 ; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lwu a0, 0(a0)
-; RV64I-NEXT:    sext.w s5, a1
-; RV64I-NEXT:    addi s3, sp, 12
-; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
 ; RV64I-NEXT:  .LBB164_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    bgeu s5, a1, .LBB164_3
+; RV64I-NEXT:    bgeu s1, a1, .LBB164_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB164_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB164_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB164_1 Depth=1
-; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    sw a0, 4(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s1
-; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_4
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    lw a0, 4(sp)
 ; RV64I-NEXT:    beqz a1, .LBB164_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst:
@@ -15083,14 +14723,12 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 2
 ; RV32I-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB201_3
@@ -15119,15 +14757,14 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 2
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB201_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -15144,14 +14781,12 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 2
 ; RV32IA-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB201_3
@@ -15180,15 +14815,14 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 2
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB201_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -15204,15 +14838,13 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    blt s1, a2, .LBB201_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB201_1 Depth=1
@@ -15221,14 +14853,13 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB201_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB201_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -15253,14 +14884,12 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 3
 ; RV32I-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB202_3
@@ -15289,7 +14918,7 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
@@ -15297,7 +14926,6 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB202_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -15314,14 +14942,12 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 3
 ; RV32IA-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB202_3
@@ -15350,7 +14976,7 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
+; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
@@ -15358,7 +14984,6 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB202_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -15374,15 +14999,13 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    blt s1, a2, .LBB202_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB202_1 Depth=1
@@ -15391,14 +15014,13 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB202_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB202_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -15417,34 +15039,30 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
 define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s4, sp, 8
-; RV32I-NEXT:    addi s5, zero, 4
-; RV32I-NEXT:    addi s6, zero, 2
+; RV32I-NEXT:    mv s4, sp
 ; RV32I-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB203_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_1 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB203_4
 ; RV32I-NEXT:    j .LBB203_5
 ; RV32I-NEXT:  .LBB203_3: # in Loop: Header=BB203_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    bnez a0, .LBB203_5
 ; RV32I-NEXT:  .LBB203_4: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_1 Depth=1
@@ -15458,57 +15076,51 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    mv a3, s1
 ; RV32I-NEXT:  .LBB203_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV32I-NEXT:    sw a1, 12(sp)
+; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s6
+; RV32I-NEXT:    addi a4, zero, 4
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
-; RV32I-NEXT:    lw a1, 12(sp)
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a1, 4(sp)
+; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB203_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    addi sp, sp, -48
-; RV32IA-NEXT:    sw ra, 44(sp)
-; RV32IA-NEXT:    sw s1, 40(sp)
-; RV32IA-NEXT:    sw s2, 36(sp)
-; RV32IA-NEXT:    sw s3, 32(sp)
-; RV32IA-NEXT:    sw s4, 28(sp)
-; RV32IA-NEXT:    sw s5, 24(sp)
-; RV32IA-NEXT:    sw s6, 20(sp)
+; RV32IA-NEXT:    addi sp, sp, -32
+; RV32IA-NEXT:    sw ra, 28(sp)
+; RV32IA-NEXT:    sw s1, 24(sp)
+; RV32IA-NEXT:    sw s2, 20(sp)
+; RV32IA-NEXT:    sw s3, 16(sp)
+; RV32IA-NEXT:    sw s4, 12(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    addi s4, sp, 8
-; RV32IA-NEXT:    addi s5, zero, 4
-; RV32IA-NEXT:    addi s6, zero, 2
+; RV32IA-NEXT:    mv s4, sp
 ; RV32IA-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB203_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_1 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a1
-; RV32IA-NEXT:    sw a2, 8(sp)
+; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB203_4
 ; RV32IA-NEXT:    j .LBB203_5
 ; RV32IA-NEXT:  .LBB203_3: # in Loop: Header=BB203_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
-; RV32IA-NEXT:    sw a2, 8(sp)
+; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    bnez a0, .LBB203_5
 ; RV32IA-NEXT:  .LBB203_4: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_1 Depth=1
@@ -15522,42 +15134,36 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    mv a3, s1
 ; RV32IA-NEXT:  .LBB203_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_1 Depth=1
-; RV32IA-NEXT:    sw a1, 12(sp)
+; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s6
+; RV32IA-NEXT:    addi a4, zero, 4
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
-; RV32IA-NEXT:    lw a1, 12(sp)
-; RV32IA-NEXT:    lw a2, 8(sp)
+; RV32IA-NEXT:    lw a1, 4(sp)
+; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB203_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s6, 20(sp)
-; RV32IA-NEXT:    lw s5, 24(sp)
-; RV32IA-NEXT:    lw s4, 28(sp)
-; RV32IA-NEXT:    lw s3, 32(sp)
-; RV32IA-NEXT:    lw s2, 36(sp)
-; RV32IA-NEXT:    lw s1, 40(sp)
-; RV32IA-NEXT:    lw ra, 44(sp)
-; RV32IA-NEXT:    addi sp, sp, 48
+; RV32IA-NEXT:    lw s4, 12(sp)
+; RV32IA-NEXT:    lw s3, 16(sp)
+; RV32IA-NEXT:    lw s2, 20(sp)
+; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw ra, 28(sp)
+; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
 ; RV64I-NEXT:    addi s3, sp, 8
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
@@ -15569,20 +15175,18 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB203_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
-; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 8(sp)
-; RV64I-NEXT:    beqz a0, .LBB203_1
-; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
-; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB203_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
@@ -15602,14 +15206,12 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 5
 ; RV32I-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB204_3
@@ -15638,15 +15240,14 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 5
+; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB204_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -15663,14 +15264,12 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 5
 ; RV32IA-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB204_3
@@ -15699,15 +15298,14 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 5
+; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB204_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -15723,15 +15321,13 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    blt s1, a2, .LBB204_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB204_1 Depth=1
@@ -15740,14 +15336,13 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB204_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB204_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -15935,14 +15530,12 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 2
 ; RV32I-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB206_3
@@ -15972,15 +15565,14 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 2
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB206_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -15997,14 +15589,12 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 2
 ; RV32IA-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB206_3
@@ -16034,15 +15624,14 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 2
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB206_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -16058,15 +15647,13 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bge s1, a2, .LBB206_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB206_1 Depth=1
@@ -16075,14 +15662,13 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB206_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB206_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -16107,14 +15693,12 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 3
 ; RV32I-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB207_3
@@ -16144,7 +15728,7 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
@@ -16152,7 +15736,6 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB207_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -16169,14 +15752,12 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 3
 ; RV32IA-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB207_3
@@ -16206,7 +15787,7 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
+; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
@@ -16214,7 +15795,6 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB207_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -16230,15 +15810,13 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bge s1, a2, .LBB207_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB207_1 Depth=1
@@ -16247,14 +15825,13 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB207_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB207_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -16273,22 +15850,18 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
 define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s4, sp, 8
-; RV32I-NEXT:    addi s5, zero, 4
-; RV32I-NEXT:    addi s6, zero, 2
+; RV32I-NEXT:    mv s4, sp
 ; RV32I-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB208_3
@@ -16301,7 +15874,7 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:  .LBB208_4: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_1 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    bnez a0, .LBB208_6
 ; RV32I-NEXT:  # %bb.5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_1 Depth=1
@@ -16315,45 +15888,39 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    mv a3, s1
 ; RV32I-NEXT:  .LBB208_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV32I-NEXT:    sw a1, 12(sp)
+; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s6
+; RV32I-NEXT:    addi a4, zero, 4
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
-; RV32I-NEXT:    lw a1, 12(sp)
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a1, 4(sp)
+; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB208_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    addi sp, sp, -48
-; RV32IA-NEXT:    sw ra, 44(sp)
-; RV32IA-NEXT:    sw s1, 40(sp)
-; RV32IA-NEXT:    sw s2, 36(sp)
-; RV32IA-NEXT:    sw s3, 32(sp)
-; RV32IA-NEXT:    sw s4, 28(sp)
-; RV32IA-NEXT:    sw s5, 24(sp)
-; RV32IA-NEXT:    sw s6, 20(sp)
+; RV32IA-NEXT:    addi sp, sp, -32
+; RV32IA-NEXT:    sw ra, 28(sp)
+; RV32IA-NEXT:    sw s1, 24(sp)
+; RV32IA-NEXT:    sw s2, 20(sp)
+; RV32IA-NEXT:    sw s3, 16(sp)
+; RV32IA-NEXT:    sw s4, 12(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    addi s4, sp, 8
-; RV32IA-NEXT:    addi s5, zero, 4
-; RV32IA-NEXT:    addi s6, zero, 2
+; RV32IA-NEXT:    mv s4, sp
 ; RV32IA-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB208_3
@@ -16366,7 +15933,7 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:  .LBB208_4: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_1 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
-; RV32IA-NEXT:    sw a2, 8(sp)
+; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    bnez a0, .LBB208_6
 ; RV32IA-NEXT:  # %bb.5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_1 Depth=1
@@ -16380,42 +15947,36 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    mv a3, s1
 ; RV32IA-NEXT:  .LBB208_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_1 Depth=1
-; RV32IA-NEXT:    sw a1, 12(sp)
+; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s6
+; RV32IA-NEXT:    addi a4, zero, 4
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
-; RV32IA-NEXT:    lw a1, 12(sp)
-; RV32IA-NEXT:    lw a2, 8(sp)
+; RV32IA-NEXT:    lw a1, 4(sp)
+; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB208_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s6, 20(sp)
-; RV32IA-NEXT:    lw s5, 24(sp)
-; RV32IA-NEXT:    lw s4, 28(sp)
-; RV32IA-NEXT:    lw s3, 32(sp)
-; RV32IA-NEXT:    lw s2, 36(sp)
-; RV32IA-NEXT:    lw s1, 40(sp)
-; RV32IA-NEXT:    lw ra, 44(sp)
-; RV32IA-NEXT:    addi sp, sp, 48
+; RV32IA-NEXT:    lw s4, 12(sp)
+; RV32IA-NEXT:    lw s3, 16(sp)
+; RV32IA-NEXT:    lw s2, 20(sp)
+; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw ra, 28(sp)
+; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
 ; RV64I-NEXT:    addi s3, sp, 8
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
@@ -16427,20 +15988,18 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB208_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
 ; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB208_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i64_acq_rel:
@@ -16460,14 +16019,12 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 5
 ; RV32I-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB209_3
@@ -16497,15 +16054,14 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 5
+; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB209_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -16522,14 +16078,12 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 5
 ; RV32IA-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB209_3
@@ -16559,15 +16113,14 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 5
+; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB209_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -16583,15 +16136,13 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bge s1, a2, .LBB209_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB209_1 Depth=1
@@ -16600,14 +16151,13 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB209_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB209_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -16793,14 +16343,12 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 2
 ; RV32I-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB211_3
@@ -16829,15 +16377,14 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 2
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB211_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -16854,14 +16401,12 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 2
 ; RV32IA-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB211_3
@@ -16890,15 +16435,14 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 2
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB211_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -16914,15 +16458,13 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bltu s1, a2, .LBB211_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB211_1 Depth=1
@@ -16931,14 +16473,13 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB211_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB211_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -16963,14 +16504,12 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 3
 ; RV32I-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB212_3
@@ -16999,7 +16538,7 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
@@ -17007,7 +16546,6 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB212_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -17024,14 +16562,12 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 3
 ; RV32IA-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB212_3
@@ -17060,7 +16596,7 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
+; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
@@ -17068,7 +16604,6 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB212_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -17084,15 +16619,13 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bltu s1, a2, .LBB212_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB212_1 Depth=1
@@ -17101,14 +16634,13 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB212_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB212_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -17127,34 +16659,30 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
 define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s4, sp, 8
-; RV32I-NEXT:    addi s5, zero, 4
-; RV32I-NEXT:    addi s6, zero, 2
+; RV32I-NEXT:    mv s4, sp
 ; RV32I-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB213_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB213_4
 ; RV32I-NEXT:    j .LBB213_5
 ; RV32I-NEXT:  .LBB213_3: # in Loop: Header=BB213_1 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a2
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    bnez a0, .LBB213_5
 ; RV32I-NEXT:  .LBB213_4: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_1 Depth=1
@@ -17168,57 +16696,51 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    mv a3, s1
 ; RV32I-NEXT:  .LBB213_7: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV32I-NEXT:    sw a1, 12(sp)
+; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s6
+; RV32I-NEXT:    addi a4, zero, 4
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
-; RV32I-NEXT:    lw a1, 12(sp)
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a1, 4(sp)
+; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB213_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    addi sp, sp, -48
-; RV32IA-NEXT:    sw ra, 44(sp)
-; RV32IA-NEXT:    sw s1, 40(sp)
-; RV32IA-NEXT:    sw s2, 36(sp)
-; RV32IA-NEXT:    sw s3, 32(sp)
-; RV32IA-NEXT:    sw s4, 28(sp)
-; RV32IA-NEXT:    sw s5, 24(sp)
-; RV32IA-NEXT:    sw s6, 20(sp)
+; RV32IA-NEXT:    addi sp, sp, -32
+; RV32IA-NEXT:    sw ra, 28(sp)
+; RV32IA-NEXT:    sw s1, 24(sp)
+; RV32IA-NEXT:    sw s2, 20(sp)
+; RV32IA-NEXT:    sw s3, 16(sp)
+; RV32IA-NEXT:    sw s4, 12(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    addi s4, sp, 8
-; RV32IA-NEXT:    addi s5, zero, 4
-; RV32IA-NEXT:    addi s6, zero, 2
+; RV32IA-NEXT:    mv s4, sp
 ; RV32IA-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB213_3
 ; RV32IA-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a1
-; RV32IA-NEXT:    sw a2, 8(sp)
+; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB213_4
 ; RV32IA-NEXT:    j .LBB213_5
 ; RV32IA-NEXT:  .LBB213_3: # in Loop: Header=BB213_1 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a2
-; RV32IA-NEXT:    sw a2, 8(sp)
+; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    bnez a0, .LBB213_5
 ; RV32IA-NEXT:  .LBB213_4: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_1 Depth=1
@@ -17232,42 +16754,36 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    mv a3, s1
 ; RV32IA-NEXT:  .LBB213_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_1 Depth=1
-; RV32IA-NEXT:    sw a1, 12(sp)
+; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s6
+; RV32IA-NEXT:    addi a4, zero, 4
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
-; RV32IA-NEXT:    lw a1, 12(sp)
-; RV32IA-NEXT:    lw a2, 8(sp)
+; RV32IA-NEXT:    lw a1, 4(sp)
+; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB213_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s6, 20(sp)
-; RV32IA-NEXT:    lw s5, 24(sp)
-; RV32IA-NEXT:    lw s4, 28(sp)
-; RV32IA-NEXT:    lw s3, 32(sp)
-; RV32IA-NEXT:    lw s2, 36(sp)
-; RV32IA-NEXT:    lw s1, 40(sp)
-; RV32IA-NEXT:    lw ra, 44(sp)
-; RV32IA-NEXT:    addi sp, sp, 48
+; RV32IA-NEXT:    lw s4, 12(sp)
+; RV32IA-NEXT:    lw s3, 16(sp)
+; RV32IA-NEXT:    lw s2, 20(sp)
+; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw ra, 28(sp)
+; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
 ; RV64I-NEXT:    addi s3, sp, 8
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
@@ -17279,20 +16795,18 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB213_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
 ; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB213_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel:
@@ -17312,14 +16826,12 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 5
 ; RV32I-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB214_3
@@ -17348,15 +16860,14 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 5
+; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB214_1
 ; RV32I-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -17373,14 +16884,12 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 5
 ; RV32IA-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB214_3
@@ -17409,15 +16918,14 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 5
+; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB214_1
 ; RV32IA-NEXT:  # %bb.8: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -17433,15 +16941,13 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bltu s1, a2, .LBB214_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB214_1 Depth=1
@@ -17450,14 +16956,13 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB214_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB214_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -17645,14 +17150,12 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 2
 ; RV32I-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB216_3
@@ -17682,15 +17185,14 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 2
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB216_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -17707,14 +17209,12 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 2
 ; RV32IA-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB216_3
@@ -17744,15 +17244,14 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 2
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB216_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -17768,15 +17267,13 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bgeu s1, a2, .LBB216_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB216_1 Depth=1
@@ -17785,14 +17282,13 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB216_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 2
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB216_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -17817,14 +17313,12 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 3
 ; RV32I-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB217_3
@@ -17854,7 +17348,7 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
+; RV32I-NEXT:    addi a4, zero, 3
 ; RV32I-NEXT:    mv a5, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
@@ -17862,7 +17356,6 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    beqz a0, .LBB217_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -17879,14 +17372,12 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 3
 ; RV32IA-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB217_3
@@ -17916,7 +17407,7 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
+; RV32IA-NEXT:    addi a4, zero, 3
 ; RV32IA-NEXT:    mv a5, zero
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
@@ -17924,7 +17415,6 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    beqz a0, .LBB217_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -17940,15 +17430,13 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bgeu s1, a2, .LBB217_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB217_1 Depth=1
@@ -17957,14 +17445,13 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB217_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB217_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
@@ -17983,22 +17470,18 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
 define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
-; RV32I-NEXT:    addi s4, sp, 8
-; RV32I-NEXT:    addi s5, zero, 4
-; RV32I-NEXT:    addi s6, zero, 2
+; RV32I-NEXT:    mv s4, sp
 ; RV32I-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB218_3
@@ -18011,7 +17494,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:  .LBB218_4: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_1 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    sw a2, 8(sp)
+; RV32I-NEXT:    sw a2, 0(sp)
 ; RV32I-NEXT:    bnez a0, .LBB218_6
 ; RV32I-NEXT:  # %bb.5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_1 Depth=1
@@ -18025,45 +17508,39 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    mv a3, s1
 ; RV32I-NEXT:  .LBB218_8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV32I-NEXT:    sw a1, 12(sp)
+; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s6
+; RV32I-NEXT:    addi a4, zero, 4
+; RV32I-NEXT:    addi a5, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
-; RV32I-NEXT:    lw a1, 12(sp)
-; RV32I-NEXT:    lw a2, 8(sp)
+; RV32I-NEXT:    lw a1, 4(sp)
+; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB218_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    addi sp, sp, -48
-; RV32IA-NEXT:    sw ra, 44(sp)
-; RV32IA-NEXT:    sw s1, 40(sp)
-; RV32IA-NEXT:    sw s2, 36(sp)
-; RV32IA-NEXT:    sw s3, 32(sp)
-; RV32IA-NEXT:    sw s4, 28(sp)
-; RV32IA-NEXT:    sw s5, 24(sp)
-; RV32IA-NEXT:    sw s6, 20(sp)
+; RV32IA-NEXT:    addi sp, sp, -32
+; RV32IA-NEXT:    sw ra, 28(sp)
+; RV32IA-NEXT:    sw s1, 24(sp)
+; RV32IA-NEXT:    sw s2, 20(sp)
+; RV32IA-NEXT:    sw s3, 16(sp)
+; RV32IA-NEXT:    sw s4, 12(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
-; RV32IA-NEXT:    addi s4, sp, 8
-; RV32IA-NEXT:    addi s5, zero, 4
-; RV32IA-NEXT:    addi s6, zero, 2
+; RV32IA-NEXT:    mv s4, sp
 ; RV32IA-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB218_3
@@ -18076,7 +17553,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:  .LBB218_4: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_1 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
-; RV32IA-NEXT:    sw a2, 8(sp)
+; RV32IA-NEXT:    sw a2, 0(sp)
 ; RV32IA-NEXT:    bnez a0, .LBB218_6
 ; RV32IA-NEXT:  # %bb.5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_1 Depth=1
@@ -18090,42 +17567,36 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    mv a3, s1
 ; RV32IA-NEXT:  .LBB218_8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_1 Depth=1
-; RV32IA-NEXT:    sw a1, 12(sp)
+; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s6
+; RV32IA-NEXT:    addi a4, zero, 4
+; RV32IA-NEXT:    addi a5, zero, 2
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
-; RV32IA-NEXT:    lw a1, 12(sp)
-; RV32IA-NEXT:    lw a2, 8(sp)
+; RV32IA-NEXT:    lw a1, 4(sp)
+; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB218_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s6, 20(sp)
-; RV32IA-NEXT:    lw s5, 24(sp)
-; RV32IA-NEXT:    lw s4, 28(sp)
-; RV32IA-NEXT:    lw s3, 32(sp)
-; RV32IA-NEXT:    lw s2, 36(sp)
-; RV32IA-NEXT:    lw s1, 40(sp)
-; RV32IA-NEXT:    lw ra, 44(sp)
-; RV32IA-NEXT:    addi sp, sp, 48
+; RV32IA-NEXT:    lw s4, 12(sp)
+; RV32IA-NEXT:    lw s3, 16(sp)
+; RV32IA-NEXT:    lw s2, 20(sp)
+; RV32IA-NEXT:    lw s1, 24(sp)
+; RV32IA-NEXT:    lw ra, 28(sp)
+; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s1, 48(sp)
-; RV64I-NEXT:    sd s2, 40(sp)
-; RV64I-NEXT:    sd s3, 32(sp)
-; RV64I-NEXT:    sd s4, 24(sp)
-; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
 ; RV64I-NEXT:    addi s3, sp, 8
-; RV64I-NEXT:    addi s4, zero, 4
-; RV64I-NEXT:    addi s5, zero, 2
 ; RV64I-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    sd a2, 8(sp)
@@ -18137,20 +17608,18 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB218_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    addi a3, zero, 4
+; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
 ; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB218_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s5, 16(sp)
-; RV64I-NEXT:    ld s4, 24(sp)
-; RV64I-NEXT:    ld s3, 32(sp)
-; RV64I-NEXT:    ld s2, 40(sp)
-; RV64I-NEXT:    ld s1, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel:
@@ -18170,14 +17639,12 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
-; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    mv s1, a2
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lw a1, 4(a0)
 ; RV32I-NEXT:    lw a2, 0(a0)
 ; RV32I-NEXT:    mv s4, sp
-; RV32I-NEXT:    addi s5, zero, 5
 ; RV32I-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a1, s1, .LBB219_3
@@ -18207,15 +17674,14 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    mv a4, s5
-; RV32I-NEXT:    mv a5, s5
+; RV32I-NEXT:    addi a4, zero, 5
+; RV32I-NEXT:    addi a5, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_8
 ; RV32I-NEXT:    lw a1, 4(sp)
 ; RV32I-NEXT:    lw a2, 0(sp)
 ; RV32I-NEXT:    beqz a0, .LBB219_1
 ; RV32I-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
@@ -18232,14 +17698,12 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw s2, 20(sp)
 ; RV32IA-NEXT:    sw s3, 16(sp)
 ; RV32IA-NEXT:    sw s4, 12(sp)
-; RV32IA-NEXT:    sw s5, 8(sp)
 ; RV32IA-NEXT:    mv s1, a2
 ; RV32IA-NEXT:    mv s2, a1
 ; RV32IA-NEXT:    mv s3, a0
 ; RV32IA-NEXT:    lw a1, 4(a0)
 ; RV32IA-NEXT:    lw a2, 0(a0)
 ; RV32IA-NEXT:    mv s4, sp
-; RV32IA-NEXT:    addi s5, zero, 5
 ; RV32IA-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a1, s1, .LBB219_3
@@ -18269,15 +17733,14 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV32IA-NEXT:    sw a1, 4(sp)
 ; RV32IA-NEXT:    mv a0, s3
 ; RV32IA-NEXT:    mv a1, s4
-; RV32IA-NEXT:    mv a4, s5
-; RV32IA-NEXT:    mv a5, s5
+; RV32IA-NEXT:    addi a4, zero, 5
+; RV32IA-NEXT:    addi a5, zero, 5
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8
 ; RV32IA-NEXT:    lw a1, 4(sp)
 ; RV32IA-NEXT:    lw a2, 0(sp)
 ; RV32IA-NEXT:    beqz a0, .LBB219_1
 ; RV32IA-NEXT:  # %bb.9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
-; RV32IA-NEXT:    lw s5, 8(sp)
 ; RV32IA-NEXT:    lw s4, 12(sp)
 ; RV32IA-NEXT:    lw s3, 16(sp)
 ; RV32IA-NEXT:    lw s2, 20(sp)
@@ -18293,15 +17756,13 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
-; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s1, a1
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    ld a2, 0(a0)
-; RV64I-NEXT:    mv s3, sp
-; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:    addi s3, sp, 8
 ; RV64I-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    sd a2, 8(sp)
 ; RV64I-NEXT:    bgeu s1, a2, .LBB219_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB219_1 Depth=1
@@ -18310,14 +17771,13 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
 ; RV64I-NEXT:    # in Loop: Header=BB219_1 Depth=1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    mv a3, s4
-; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    addi a3, zero, 5
+; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_8
-; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    ld a2, 8(sp)
 ; RV64I-NEXT:    beqz a0, .LBB219_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)

diff --git a/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll b/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
index 849e18a81bbd669e78cb8166e61bb824ef6814a7..9a68f0006668dff9c0f368524a4f82c36d0fbd1d 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
+++ b/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
@@ -36,12 +36,12 @@ define float @caller_onstack_f32_noop(float %a) nounwind {
 ; RV32IF-NEXT:    lui a0, 264704
 ; RV32IF-NEXT:    sw a0, 0(sp)
 ; RV32IF-NEXT:    addi a0, zero, 1
-; RV32IF-NEXT:    addi a2, zero, 2
-; RV32IF-NEXT:    addi a4, zero, 3
-; RV32IF-NEXT:    addi a6, zero, 4
 ; RV32IF-NEXT:    mv a1, zero
+; RV32IF-NEXT:    addi a2, zero, 2
 ; RV32IF-NEXT:    mv a3, zero
+; RV32IF-NEXT:    addi a4, zero, 3
 ; RV32IF-NEXT:    mv a5, zero
+; RV32IF-NEXT:    addi a6, zero, 4
 ; RV32IF-NEXT:    mv a7, zero
 ; RV32IF-NEXT:    call onstack_f32_noop
 ; RV32IF-NEXT:    lw ra, 12(sp)
@@ -63,12 +63,12 @@ define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fadd.s ft0, ft0, ft1
 ; RV32IF-NEXT:    fsw ft0, 0(sp)
 ; RV32IF-NEXT:    addi a0, zero, 1
-; RV32IF-NEXT:    addi a2, zero, 2
-; RV32IF-NEXT:    addi a4, zero, 3
-; RV32IF-NEXT:    addi a6, zero, 4
 ; RV32IF-NEXT:    mv a1, zero
+; RV32IF-NEXT:    addi a2, zero, 2
 ; RV32IF-NEXT:    mv a3, zero
+; RV32IF-NEXT:    addi a4, zero, 3
 ; RV32IF-NEXT:    mv a5, zero
+; RV32IF-NEXT:    addi a6, zero, 4
 ; RV32IF-NEXT:    mv a7, zero
 ; RV32IF-NEXT:    call onstack_f32_noop
 ; RV32IF-NEXT:    lw ra, 12(sp)

diff --git a/test/CodeGen/RISCV/calling-conv.ll b/test/CodeGen/RISCV/calling-conv.ll
index 56f1de682d7df15107597d0b05397986b77e8322..8de776377605d439a1fc288893cb1eec102f20f7 100644 (file)
--- a/test/CodeGen/RISCV/calling-conv.ll
+++ b/test/CodeGen/RISCV/calling-conv.ll
@@ -83,11 +83,11 @@ define i32 @caller_scalars() nounwind {
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
+; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 4
-; RV32I-FPELIM-NEXT:    lui a6, 262464
-; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    mv a5, zero
+; RV32I-FPELIM-NEXT:    lui a6, 262464
 ; RV32I-FPELIM-NEXT:    call callee_scalars
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
@@ -101,11 +101,11 @@ define i32 @caller_scalars() nounwind {
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
+; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 4
-; RV32I-WITHFP-NEXT:    lui a6, 262464
-; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    mv a5, zero
+; RV32I-WITHFP-NEXT:    lui a6, 262464
 ; RV32I-WITHFP-NEXT:    call callee_scalars
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
@@ -296,6 +296,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-FPELIM-NEXT:    sw zero, 44(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 8
 ; RV32I-FPELIM-NEXT:    sw a0, 40(sp)
+; RV32I-FPELIM-NEXT:    addi a7, sp, 40
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a2, zero, 3
@@ -303,7 +304,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 5
 ; RV32I-FPELIM-NEXT:    addi a5, zero, 6
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 7
-; RV32I-FPELIM-NEXT:    addi a7, sp, 40
 ; RV32I-FPELIM-NEXT:    call callee_large_scalars_exhausted_regs
 ; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 64
@@ -329,6 +329,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 8
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
+; RV32I-WITHFP-NEXT:    addi a7, s0, -24
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a2, zero, 3
@@ -336,7 +337,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 5
 ; RV32I-WITHFP-NEXT:    addi a5, zero, 6
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 7
-; RV32I-WITHFP-NEXT:    addi a7, s0, -24
 ; RV32I-WITHFP-NEXT:    call callee_large_scalars_exhausted_regs
 ; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
@@ -459,10 +459,10 @@ define i32 @caller_many_scalars() nounwind {
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a2, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 4
+; RV32I-FPELIM-NEXT:    mv a4, zero
 ; RV32I-FPELIM-NEXT:    addi a5, zero, 5
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 6
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 7
-; RV32I-FPELIM-NEXT:    mv a4, zero
 ; RV32I-FPELIM-NEXT:    call callee_many_scalars
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
@@ -481,10 +481,10 @@ define i32 @caller_many_scalars() nounwind {
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a2, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 4
+; RV32I-WITHFP-NEXT:    mv a4, zero
 ; RV32I-WITHFP-NEXT:    addi a5, zero, 5
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 6
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 7
-; RV32I-WITHFP-NEXT:    mv a4, zero
 ; RV32I-WITHFP-NEXT:    call callee_many_scalars
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
@@ -734,9 +734,9 @@ define void @caller_aligned_stack() nounwind {
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 688509
 ; RV32I-FPELIM-NEXT:    addi a5, a0, -2048
+; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 11
-; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 4
@@ -780,9 +780,9 @@ define void @caller_aligned_stack() nounwind {
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 688509
 ; RV32I-WITHFP-NEXT:    addi a5, a0, -2048
+; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 11
-; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 4

diff --git a/test/CodeGen/RISCV/double-calling-conv.ll b/test/CodeGen/RISCV/double-calling-conv.ll
index 5e9382fdf696ce4f8bc6901dba21c331a8605d04..2fe79418922eddac42ec30776555185e2be5c614 100644 (file)
--- a/test/CodeGen/RISCV/double-calling-conv.ll
+++ b/test/CodeGen/RISCV/double-calling-conv.ll
@@ -95,8 +95,8 @@ define double @caller_double_split_reg_stack() nounwind {
 ; RV32IFD-NEXT:    lw a6, 20(sp)
 ; RV32IFD-NEXT:    addi a0, zero, 1
 ; RV32IFD-NEXT:    addi a1, zero, 2
-; RV32IFD-NEXT:    addi a3, zero, 3
 ; RV32IFD-NEXT:    mv a2, zero
+; RV32IFD-NEXT:    addi a3, zero, 3
 ; RV32IFD-NEXT:    mv a4, zero
 ; RV32IFD-NEXT:    call callee_double_split_reg_stack
 ; RV32IFD-NEXT:    lw ra, 28(sp)
@@ -138,12 +138,12 @@ define double @caller_double_stack() nounwind {
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    addi a0, zero, 1
-; RV32IFD-NEXT:    addi a2, zero, 2
-; RV32IFD-NEXT:    addi a4, zero, 3
-; RV32IFD-NEXT:    addi a6, zero, 4
 ; RV32IFD-NEXT:    mv a1, zero
+; RV32IFD-NEXT:    addi a2, zero, 2
 ; RV32IFD-NEXT:    mv a3, zero
+; RV32IFD-NEXT:    addi a4, zero, 3
 ; RV32IFD-NEXT:    mv a5, zero
+; RV32IFD-NEXT:    addi a6, zero, 4
 ; RV32IFD-NEXT:    mv a7, zero
 ; RV32IFD-NEXT:    call callee_double_stack
 ; RV32IFD-NEXT:    lw ra, 28(sp)

diff --git a/test/CodeGen/RISCV/imm.ll b/test/CodeGen/RISCV/imm.ll
index 872b6d5a9864b1b42c81e4573681b63f7198e2d6..b733b5921658dc575ce1ef923a72aa8d13de1df3 100644 (file)
--- a/test/CodeGen/RISCV/imm.ll
+++ b/test/CodeGen/RISCV/imm.ll
@@ -142,8 +142,8 @@ define i64 @imm64_2() nounwind {
 define i64 @imm64_3() nounwind {
 ; RV32I-LABEL: imm64_3:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a1, zero, 1
 ; RV32I-NEXT:    mv a0, zero
+; RV32I-NEXT:    addi a1, zero, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_3:
@@ -157,8 +157,8 @@ define i64 @imm64_3() nounwind {
 define i64 @imm64_4() nounwind {
 ; RV32I-LABEL: imm64_4:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    mv a0, zero
+; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_4:
@@ -172,8 +172,8 @@ define i64 @imm64_4() nounwind {
 define i64 @imm64_5() nounwind {
 ; RV32I-LABEL: imm64_5:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    mv a0, zero
+; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_5:
@@ -249,7 +249,7 @@ define i64 @imm64_9() nounwind {
 ; RV32I-LABEL: imm64_9:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, zero, -1
-; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    addi  a1, zero, -1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_9:

diff --git a/test/CodeGen/RISCV/jumptable.ll b/test/CodeGen/RISCV/jumptable.ll
index f54f51edadae3e3adac327bf0341f788a9f00fb8..f849dc959abc4844b6089c92453d18c3c0461526 100644 (file)
--- a/test/CodeGen/RISCV/jumptable.ll
+++ b/test/CodeGen/RISCV/jumptable.ll
@@ -8,31 +8,31 @@ define void @jt(i32 %in, i32* %out) {
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    blt a2, a0, .LBB0_4
 ; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    addi a3, zero, 1
-; RV32I-NEXT:    beq a0, a3, .LBB0_7
+; RV32I-NEXT:    addi a2, zero, 1
+; RV32I-NEXT:    beq a0, a2, .LBB0_7
 ; RV32I-NEXT:  # %bb.2: # %entry
-; RV32I-NEXT:    bne a0, a2, .LBB0_9
+; RV32I-NEXT:    addi a2, zero, 2
+; RV32I-NEXT:    bne a0, a2, .LBB0_10
 ; RV32I-NEXT:  # %bb.3: # %bb2
 ; RV32I-NEXT:    addi a0, zero, 3
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:    ret
+; RV32I-NEXT:    j .LBB0_9
 ; RV32I-NEXT:  .LBB0_4: # %entry
-; RV32I-NEXT:    addi a3, zero, 3
-; RV32I-NEXT:    beq a0, a3, .LBB0_8
+; RV32I-NEXT:    addi a2, zero, 3
+; RV32I-NEXT:    beq a0, a2, .LBB0_8
 ; RV32I-NEXT:  # %bb.5: # %entry
 ; RV32I-NEXT:    addi a2, zero, 4
-; RV32I-NEXT:    bne a0, a2, .LBB0_9
+; RV32I-NEXT:    bne a0, a2, .LBB0_10
 ; RV32I-NEXT:  # %bb.6: # %bb4
 ; RV32I-NEXT:    addi a0, zero, 1
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:    ret
+; RV32I-NEXT:    j .LBB0_9
 ; RV32I-NEXT:  .LBB0_7: # %bb1
 ; RV32I-NEXT:    addi a0, zero, 4
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:    ret
+; RV32I-NEXT:    j .LBB0_9
 ; RV32I-NEXT:  .LBB0_8: # %bb3
-; RV32I-NEXT:    sw a2, 0(a1)
+; RV32I-NEXT:    addi a0, zero, 2
 ; RV32I-NEXT:  .LBB0_9: # %exit
+; RV32I-NEXT:    sw a0, 0(a1)
+; RV32I-NEXT:  .LBB0_10: # %exit
 ; RV32I-NEXT:    ret
 entry:
   switch i32 %in, label %exit [

diff --git a/test/CodeGen/RISCV/remat.ll b/test/CodeGen/RISCV/remat.ll
index 3b146615bf0fb05057e1c1b9032a5897b1560b15..a1b8a6ce9e032c8a6a736e980fe43b76d0636480 100644 (file)
--- a/test/CodeGen/RISCV/remat.ll
+++ b/test/CodeGen/RISCV/remat.ll
@@ -36,78 +36,77 @@ define i32 @test() nounwind {
 ; RV32I-NEXT:    sw s9, 8(sp)
 ; RV32I-NEXT:    sw s10, 4(sp)
 ; RV32I-NEXT:    sw s11, 0(sp)
-; RV32I-NEXT:    lui s3, %hi(a)
-; RV32I-NEXT:    lw a0, %lo(a)(s3)
+; RV32I-NEXT:    lui s9, %hi(a)
+; RV32I-NEXT:    lw a0, %lo(a)(s9)
 ; RV32I-NEXT:    beqz a0, .LBB0_11
 ; RV32I-NEXT:  # %bb.1: # %for.body.preheader
-; RV32I-NEXT:    lui s5, %hi(k)
-; RV32I-NEXT:    lui s6, %hi(j)
-; RV32I-NEXT:    lui s7, %hi(i)
-; RV32I-NEXT:    lui s9, %hi(g)
-; RV32I-NEXT:    lui s10, %hi(f)
-; RV32I-NEXT:    lui s1, %hi(e)
-; RV32I-NEXT:    lui s8, %hi(d)
-; RV32I-NEXT:    addi s11, zero, 32
-; RV32I-NEXT:    lui s2, %hi(c)
-; RV32I-NEXT:    lui s4, %hi(b)
+; RV32I-NEXT:    lui s2, %hi(l)
+; RV32I-NEXT:    lui s3, %hi(k)
+; RV32I-NEXT:    lui s4, %hi(j)
+; RV32I-NEXT:    lui s5, %hi(i)
+; RV32I-NEXT:    lui s7, %hi(g)
+; RV32I-NEXT:    lui s8, %hi(f)
+; RV32I-NEXT:    lui s10, %hi(e)
+; RV32I-NEXT:    lui s1, %hi(d)
+; RV32I-NEXT:    lui s11, %hi(c)
+; RV32I-NEXT:    lui s6, %hi(b)
 ; RV32I-NEXT:  .LBB0_2: # %for.body
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    lui a1, %hi(l)
-; RV32I-NEXT:    lw a1, %lo(l)(a1)
+; RV32I-NEXT:    lw a1, %lo(l)(s2)
 ; RV32I-NEXT:    beqz a1, .LBB0_4
 ; RV32I-NEXT:  # %bb.3: # %if.then
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a4, %lo(e)(s1)
-; RV32I-NEXT:    lw a3, %lo(d)(s8)
-; RV32I-NEXT:    lw a2, %lo(c)(s2)
-; RV32I-NEXT:    lw a1, %lo(b)(s4)
-; RV32I-NEXT:    mv a5, s11
+; RV32I-NEXT:    lw a4, %lo(e)(s10)
+; RV32I-NEXT:    lw a3, %lo(d)(s1)
+; RV32I-NEXT:    lw a2, %lo(c)(s11)
+; RV32I-NEXT:    lw a1, %lo(b)(s6)
+; RV32I-NEXT:    addi a5, zero, 32
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_4: # %if.end
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a0, %lo(k)(s5)
+; RV32I-NEXT:    lw a0, %lo(k)(s3)
 ; RV32I-NEXT:    beqz a0, .LBB0_6
 ; RV32I-NEXT:  # %bb.5: # %if.then3
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a4, %lo(f)(s10)
-; RV32I-NEXT:    lw a3, %lo(e)(s1)
-; RV32I-NEXT:    lw a2, %lo(d)(s8)
-; RV32I-NEXT:    lw a1, %lo(c)(s2)
-; RV32I-NEXT:    lw a0, %lo(b)(s4)
+; RV32I-NEXT:    lw a4, %lo(f)(s8)
+; RV32I-NEXT:    lw a3, %lo(e)(s10)
+; RV32I-NEXT:    lw a2, %lo(d)(s1)
+; RV32I-NEXT:    lw a1, %lo(c)(s11)
+; RV32I-NEXT:    lw a0, %lo(b)(s6)
 ; RV32I-NEXT:    addi a5, zero, 64
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_6: # %if.end5
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a0, %lo(j)(s6)
+; RV32I-NEXT:    lw a0, %lo(j)(s4)
 ; RV32I-NEXT:    beqz a0, .LBB0_8
 ; RV32I-NEXT:  # %bb.7: # %if.then7
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a4, %lo(g)(s9)
-; RV32I-NEXT:    lw a3, %lo(f)(s10)
-; RV32I-NEXT:    lw a2, %lo(e)(s1)
-; RV32I-NEXT:    lw a1, %lo(d)(s8)
-; RV32I-NEXT:    lw a0, %lo(c)(s2)
-; RV32I-NEXT:    mv a5, s11
+; RV32I-NEXT:    lw a4, %lo(g)(s7)
+; RV32I-NEXT:    lw a3, %lo(f)(s8)
+; RV32I-NEXT:    lw a2, %lo(e)(s10)
+; RV32I-NEXT:    lw a1, %lo(d)(s1)
+; RV32I-NEXT:    lw a0, %lo(c)(s11)
+; RV32I-NEXT:    addi a5, zero, 32
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_8: # %if.end9
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a0, %lo(i)(s7)
+; RV32I-NEXT:    lw a0, %lo(i)(s5)
 ; RV32I-NEXT:    beqz a0, .LBB0_10
 ; RV32I-NEXT:  # %bb.9: # %if.then11
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lui a0, %hi(h)
 ; RV32I-NEXT:    lw a4, %lo(h)(a0)
-; RV32I-NEXT:    lw a3, %lo(g)(s9)
-; RV32I-NEXT:    lw a2, %lo(f)(s10)
-; RV32I-NEXT:    lw a1, %lo(e)(s1)
-; RV32I-NEXT:    lw a0, %lo(d)(s8)
-; RV32I-NEXT:    mv a5, s11
+; RV32I-NEXT:    lw a3, %lo(g)(s7)
+; RV32I-NEXT:    lw a2, %lo(f)(s8)
+; RV32I-NEXT:    lw a1, %lo(e)(s10)
+; RV32I-NEXT:    lw a0, %lo(d)(s1)
+; RV32I-NEXT:    addi a5, zero, 32
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_10: # %for.inc
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a0, %lo(a)(s3)
+; RV32I-NEXT:    lw a0, %lo(a)(s9)
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    sw a0, %lo(a)(s3)
+; RV32I-NEXT:    sw a0, %lo(a)(s9)
 ; RV32I-NEXT:    bnez a0, .LBB0_2
 ; RV32I-NEXT:  .LBB0_11: # %for.end
 ; RV32I-NEXT:    addi a0, zero, 1

diff --git a/test/CodeGen/RISCV/vararg.ll b/test/CodeGen/RISCV/vararg.ll
index 4dd73dc75e776faac99786fd8743e0fa717eedde..60286a76e041c18be711d7a105c4e38bdf8c5bbe 100644 (file)
--- a/test/CodeGen/RISCV/vararg.ll
+++ b/test/CodeGen/RISCV/vararg.ll
@@ -185,9 +185,9 @@ define void @va1_caller() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
+; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    lui a3, 261888
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 2
-; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    call va1
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
@@ -199,9 +199,9 @@ define void @va1_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
+; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    lui a3, 261888
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 2
-; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    call va1
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
@@ -335,8 +335,8 @@ define void @va2_caller() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a3, 261888
 ; RV32I-FPELIM-NEXT:    mv a2, zero
+; RV32I-FPELIM-NEXT:    lui a3, 261888
 ; RV32I-FPELIM-NEXT:    call va2
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
@@ -348,8 +348,8 @@ define void @va2_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a3, 261888
 ; RV32I-WITHFP-NEXT:    mv a2, zero
+; RV32I-WITHFP-NEXT:    lui a3, 261888
 ; RV32I-WITHFP-NEXT:    call va2
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
@@ -498,10 +498,10 @@ define void @va3_caller() nounwind {
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 2
-; RV32I-FPELIM-NEXT:    lui a2, 261888
-; RV32I-FPELIM-NEXT:    lui a5, 262144
 ; RV32I-FPELIM-NEXT:    mv a1, zero
+; RV32I-FPELIM-NEXT:    lui a2, 261888
 ; RV32I-FPELIM-NEXT:    mv a4, zero
+; RV32I-FPELIM-NEXT:    lui a5, 262144
 ; RV32I-FPELIM-NEXT:    call va3
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
@@ -514,10 +514,10 @@ define void @va3_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 2
-; RV32I-WITHFP-NEXT:    lui a2, 261888
-; RV32I-WITHFP-NEXT:    lui a5, 262144
 ; RV32I-WITHFP-NEXT:    mv a1, zero
+; RV32I-WITHFP-NEXT:    lui a2, 261888
 ; RV32I-WITHFP-NEXT:    mv a4, zero
+; RV32I-WITHFP-NEXT:    lui a5, 262144
 ; RV32I-WITHFP-NEXT:    call va3
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
@@ -707,9 +707,9 @@ define void @va5_aligned_stack_caller() nounwind {
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 688509
 ; RV32I-FPELIM-NEXT:    addi a6, a0, -2048
+; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 11
-; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 4
@@ -752,9 +752,9 @@ define void @va5_aligned_stack_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 688509
 ; RV32I-WITHFP-NEXT:    addi a6, a0, -2048
+; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 11
-; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 4