if (N0.isUndef() || N1.isUndef())
return DAG.getConstant(0, DL, VT);
+ // fold (sub_sat x, x) -> 0
+ if (N0 == N1)
+ return DAG.getConstant(0, DL, VT);
+
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
// fold (sub_sat c1, c2) -> c3
; CHECK-LABEL: combine_self_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movl %edi, %ecx
-; CHECK-NEXT: subl %edi, %ecx
-; CHECK-NEXT: setns %al
-; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-NEXT: subl %edi, %edi
-; CHECK-NEXT: cmovnol %edi, %eax
; CHECK-NEXT: retq
%1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 %a0)
ret i32 %1
define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
; SSE-LABEL: combine_self_v8i16:
; SSE: # %bb.0:
-; SSE-NEXT: psubsw %xmm0, %xmm0
+; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_self_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpsubsw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
ret <8 x i16> %1
; CHECK-LABEL: combine_self_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: subl %edi, %edi
-; CHECK-NEXT: cmovael %edi, %eax
; CHECK-NEXT: retq
%1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 %a0)
ret i32 %1
define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
; SSE-LABEL: combine_self_v8i16:
; SSE: # %bb.0:
-; SSE-NEXT: psubusw %xmm0, %xmm0
+; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_self_v8i16:
; AVX: # %bb.0:
-; AVX-NEXT: vpsubusw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
ret <8 x i16> %1