[RISCV] Specify registers used for exception handling

Implements the handling of __builtin_eh_return_regno().

Differential Revision: https://reviews.llvm.org/D63417
Patch by Edward Jones.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@365305 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Basic/Targets/RISCV.h b/lib/Basic/Targets/RISCV.h
index 4fa696953e32680d44fad82de596f09766a7ecf8..bc814b79ce51680154e68489d4da036ce607e8a1 100644 (file)
--- a/lib/Basic/Targets/RISCV.h
+++ b/lib/Basic/Targets/RISCV.h
@@ -57,6 +57,15 @@ public:
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
+  int getEHDataRegisterNumber(unsigned RegNo) const override {
+    if (RegNo == 0)
+      return 10;
+    else if (RegNo == 1)
+      return 11;
+    else
+      return -1;
+  }
+
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,

diff --git a/test/CodeGen/builtins-riscv.c b/test/CodeGen/builtins-riscv.c
new file mode 100644 (file)
index 0000000..5297c42
--- /dev/null
+++ b/test/CodeGen/builtins-riscv.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -Wall -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple riscv64 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+void test_eh_return_data_regno() {
+  // CHECK: store volatile i32 10
+  // CHECK: store volatile i32 11
+  volatile int res;
+  res = __builtin_eh_return_data_regno(0);
+  res = __builtin_eh_return_data_regno(1);
+}