[DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.

Summary:
Add missing vector write of vector read reduction, i.e.:

(insert_vector_elt x (extract_vector_elt x idx) idx) to x

Reviewers: spatel, RKSimon, efriedma

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308617 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 535b272f793f0a19a78dc0062ce32f8a6dd53e83..50cad23a00a2b5e2b674ae045ab6e82702300ec6 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13572,6 +13572,12 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
 
   EVT VT = InVec.getValueType();
 
+  // Remove redundant insertions:
+  // (insert_vector_elt x (extract_vector_elt x idx) idx) -> x
+  if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+      InVec == InVal->getOperand(0) && EltNo == InVal->getOperand(1))
+    return InVec;
+
   // Check that we know which element is being inserted
   if (!isa<ConstantSDNode>(EltNo))
     return SDValue();

diff --git a/test/CodeGen/X86/vector-shift-ashr-256.ll b/test/CodeGen/X86/vector-shift-ashr-256.ll
index 6bb57d8f5f7120d8631692a21c9c73760f453047..d21a29770cfd2fc8d70bceb6bfb6b3f8883a4451 100644 (file)
--- a/test/CodeGen/X86/vector-shift-ashr-256.ll
+++ b/test/CodeGen/X86/vector-shift-ashr-256.ll
@@ -708,8 +708,6 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
 ;
 ; X32-AVX1-LABEL: splatvar_shift_v4i64:
 ; X32-AVX1:       # BB#0:
-; X32-AVX1-NEXT:    vpextrd $1, %xmm1, %eax
-; X32-AVX1-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
 ; X32-AVX1-NEXT:    vpsrlq %xmm1, %xmm2, %xmm2
 ; X32-AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
@@ -724,8 +722,6 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
 ;
 ; X32-AVX2-LABEL: splatvar_shift_v4i64:
 ; X32-AVX2:       # BB#0:
-; X32-AVX2-NEXT:    vpextrd $1, %xmm1, %eax
-; X32-AVX2-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,2147483648,0,2147483648,0,2147483648,0,2147483648]
 ; X32-AVX2-NEXT:    vpsrlq %xmm1, %ymm2, %ymm2
 ; X32-AVX2-NEXT:    vpsrlq %xmm1, %ymm0, %ymm0

diff --git a/test/CodeGen/X86/vector-shift-lshr-256.ll b/test/CodeGen/X86/vector-shift-lshr-256.ll
index 46be36b76e98444bf0eb836a1612c3be18ac0acb..86bd6f0bc21270fe85a350025426fa2fc3057dc1 100644 (file)
--- a/test/CodeGen/X86/vector-shift-lshr-256.ll
+++ b/test/CodeGen/X86/vector-shift-lshr-256.ll
@@ -562,8 +562,6 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
 ;
 ; X32-AVX1-LABEL: splatvar_shift_v4i64:
 ; X32-AVX1:       # BB#0:
-; X32-AVX1-NEXT:    vpextrd $1, %xmm1, %eax
-; X32-AVX1-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; X32-AVX1-NEXT:    vpsrlq %xmm1, %xmm2, %xmm2
 ; X32-AVX1-NEXT:    vpsrlq %xmm1, %xmm0, %xmm0
@@ -572,8 +570,6 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
 ;
 ; X32-AVX2-LABEL: splatvar_shift_v4i64:
 ; X32-AVX2:       # BB#0:
-; X32-AVX2-NEXT:    vpextrd $1, %xmm1, %eax
-; X32-AVX2-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX2-NEXT:    vpsrlq %xmm1, %ymm0, %ymm0
 ; X32-AVX2-NEXT:    retl
   %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer

diff --git a/test/CodeGen/X86/vector-shift-shl-256.ll b/test/CodeGen/X86/vector-shift-shl-256.ll
index 4a134f440a785d4428099dcdc54b7f551e191457..d4f1a8b61f01994416f988dd938363acd2283cab 100644 (file)
--- a/test/CodeGen/X86/vector-shift-shl-256.ll
+++ b/test/CodeGen/X86/vector-shift-shl-256.ll
@@ -506,8 +506,6 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
 ;
 ; X32-AVX1-LABEL: splatvar_shift_v4i64:
 ; X32-AVX1:       # BB#0:
-; X32-AVX1-NEXT:    vpextrd $1, %xmm1, %eax
-; X32-AVX1-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; X32-AVX1-NEXT:    vpsllq %xmm1, %xmm2, %xmm2
 ; X32-AVX1-NEXT:    vpsllq %xmm1, %xmm0, %xmm0
@@ -516,8 +514,6 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
 ;
 ; X32-AVX2-LABEL: splatvar_shift_v4i64:
 ; X32-AVX2:       # BB#0:
-; X32-AVX2-NEXT:    vpextrd $1, %xmm1, %eax
-; X32-AVX2-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX2-NEXT:    vpsllq %xmm1, %ymm0, %ymm0
 ; X32-AVX2-NEXT:    retl
   %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer

diff --git a/test/CodeGen/X86/vector-shuffle-512-v8.ll b/test/CodeGen/X86/vector-shuffle-512-v8.ll
index d0b7e4eb205c6f22f9a2707ebd899d2bb15a737a..542f30dc0d23c0a4afbc85d5bf6d12c34e326b13 100644 (file)
--- a/test/CodeGen/X86/vector-shuffle-512-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-512-v8.ll
@@ -2735,8 +2735,6 @@ define <2 x i64> @test_v8i64_2_5 (<8 x i64> %v) {
 ; AVX512F-32-LABEL: test_v8i64_2_5:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    vextracti32x4 $1, %zmm0, %xmm1
-; AVX512F-32-NEXT:    vpextrd $1, %xmm1, %eax
-; AVX512F-32-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vextracti32x4 $2, %zmm0, %xmm0
 ; AVX512F-32-NEXT:    vpextrd $2, %xmm0, %eax
 ; AVX512F-32-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1