[InstCombine] Regenerate test pr17827. NFCI.

Prep work for upcoming patch D63505.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364224 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstCombine/pr17827.ll b/test/Transforms/InstCombine/pr17827.ll
index e9312fceedafaaf82f7eb278165ad6d05673906e..1bd5c5e879a77e94dd0798378e337d5e780cd5de 100644 (file)
--- a/test/Transforms/InstCombine/pr17827.ll
+++ b/test/Transforms/InstCombine/pr17827.ll
@@ -4,7 +4,7 @@
 ; With left shift, the comparison should not be modified.
 define i1 @test_shift_and_cmp_not_changed1(i8 %p) {
 ; CHECK-LABEL: @test_shift_and_cmp_not_changed1(
-; CHECK-NEXT:    [[SHLP:%.*]] = shl i8 %p, 5
+; CHECK-NEXT:    [[SHLP:%.*]] = shl i8 [[P:%.*]], 5
 ; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[SHLP]], -64
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
 ; CHECK-NEXT:    ret i1 [[CMP]]
@@ -18,7 +18,7 @@ define i1 @test_shift_and_cmp_not_changed1(i8 %p) {
 ; With arithmetic right shift, the comparison should not be modified.
 define i1 @test_shift_and_cmp_not_changed2(i8 %p) {
 ; CHECK-LABEL: @test_shift_and_cmp_not_changed2(
-; CHECK-NEXT:    [[SHLP:%.*]] = ashr i8 %p, 5
+; CHECK-NEXT:    [[SHLP:%.*]] = ashr i8 [[P:%.*]], 5
 ; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[SHLP]], -64
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
 ; CHECK-NEXT:    ret i1 [[CMP]]
@@ -33,7 +33,7 @@ define i1 @test_shift_and_cmp_not_changed2(i8 %p) {
 ; The extra input parameter should be optimized away.
 define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
 ; CHECK-LABEL: @test_shift_and_cmp_changed1(
-; CHECK-NEXT:    [[ANDP:%.*]] = shl i8 %p, 5
+; CHECK-NEXT:    [[ANDP:%.*]] = shl i8 [[P:%.*]], 5
 ; CHECK-NEXT:    [[SHL:%.*]] = and i8 [[ANDP]], -64
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[SHL]], 32
 ; CHECK-NEXT:    ret i1 [[CMP]]
@@ -66,7 +66,7 @@ define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
 ; Unsigned compare allows a transformation to compare against 0.
 define i1 @test_shift_and_cmp_changed2(i8 %p) {
 ; CHECK-LABEL: @test_shift_and_cmp_changed2(
-; CHECK-NEXT:    [[ANDP:%.*]] = and i8 %p, 6
+; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[P:%.*]], 6
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[ANDP]], 0
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
@@ -78,7 +78,7 @@ define i1 @test_shift_and_cmp_changed2(i8 %p) {
 
 define <2 x i1> @test_shift_and_cmp_changed2_vec(<2 x i8> %p) {
 ; CHECK-LABEL: @test_shift_and_cmp_changed2_vec(
-; CHECK-NEXT:    [[ANDP:%.*]] = and <2 x i8> %p, <i8 6, i8 6>
+; CHECK-NEXT:    [[ANDP:%.*]] = and <2 x i8> [[P:%.*]], <i8 6, i8 6>
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i8> [[ANDP]], zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[CMP]]
 ;
@@ -91,7 +91,7 @@ define <2 x i1> @test_shift_and_cmp_changed2_vec(<2 x i8> %p) {
 ; nsw on the shift should not affect the comparison.
 define i1 @test_shift_and_cmp_changed3(i8 %p) {
 ; CHECK-LABEL: @test_shift_and_cmp_changed3(
-; CHECK-NEXT:    [[SHLP:%.*]] = shl nsw i8 %p, 5
+; CHECK-NEXT:    [[SHLP:%.*]] = shl nsw i8 [[P:%.*]], 5
 ; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[SHLP]], -64
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
 ; CHECK-NEXT:    ret i1 [[CMP]]