AMDGPU: Fix assert on n inline asm constraint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310515 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 36028f7c60e90668312a20d2bb536c4a8acab0d7..ec1e53ac82653575badadfd9519a73b610d50c41 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1017,20 +1017,29 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                        unsigned AsmVariant,
                                        const char *ExtraCode, raw_ostream &O) {
+  // First try the generic code, which knows about modifiers like 'c' and 'n'.
+  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
+    return false;
+
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0)
       return true; // Unknown modifier.
 
     switch (ExtraCode[0]) {
-    default:
-      // See if this is a generic print operand
-      return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
     case 'r':
       break;
+    default:
+      return true;
     }
   }
 
-  AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
-                   *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
-  return false;
+  // TODO: Should be able to support other operand types like globals.
+  const MachineOperand &MO = MI->getOperand(OpNo);
+  if (MO.isReg()) {
+    AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
+                                       *MF->getSubtarget().getRegisterInfo());
+    return false;
+  }
+
+  return true;
 }

diff --git a/test/CodeGen/AMDGPU/inline-asm.ll b/test/CodeGen/AMDGPU/inline-asm.ll
index 75826d530cb047481d5aefa6546497dcf3928a22..2856212bc8993dfda77a2c3c52f100c6ac6fcad4 100644 (file)
--- a/test/CodeGen/AMDGPU/inline-asm.ll
+++ b/test/CodeGen/AMDGPU/inline-asm.ll
@@ -246,3 +246,19 @@ entry:
   store i32 %add, i32 addrspace(1)* undef
   ret void
 }
+
+; CHECK-LABEL: {{^}}asm_constraint_c_n:
+; CHECK: s_trap 10{{$}}
+define amdgpu_kernel void @asm_constraint_c_n()  {
+entry:
+  tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1
+  ret void
+}
+
+; CHECK-LABEL: {{^}}asm_constraint_n_n:
+; CHECK: s_trap -10{{$}}
+define amdgpu_kernel void @asm_constraint_n_n()  {
+entry:
+  tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
+  ret void
+}