[MIR-Canon] Don't do vreg skip for independent instructions if there are none.

We don't want to create vregs if there is nothing to use them for. That causes
verifier errors.

Differential Revision: https://reviews.llvm.org/D62740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362247 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MIRCanonicalizerPass.cpp b/lib/CodeGen/MIRCanonicalizerPass.cpp
index a4097232d7d5921b0b59a0d7c6fb499926f3415d..c7d1131d7b8a453b84ddad3145e167cd1f550370 100644 (file)
--- a/lib/CodeGen/MIRCanonicalizerPass.cpp
+++ b/lib/CodeGen/MIRCanonicalizerPass.cpp
@@ -743,7 +743,8 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
   // of the MachineBasicBlock so that they are named in the order that we sorted
   // them alphabetically. Eventually we wont need SkipVRegs because we will use
   // named vregs instead.
-  NVC.SkipVRegs();
+  if (IdempotentInstCount)
+    NVC.SkipVRegs();
 
   auto MII = MBB->begin();
   for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {

diff --git a/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir b/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
index abb2dde4d9e0bffa273b4b7da762bfdab5f8a86f..629f7aefd6aff954970f4a22c1895aebef841b38 100644 (file)
--- a/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
+++ b/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
@@ -1,4 +1,5 @@
 # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
 
 # Previously getReservedRegs was called before parsing
 # machineFunctionInfo, but the AMDGPU implementation depends on