[AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions

These instructions are added to AArch64 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336913 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index f4bbbbeb0eb249a1940c57e883f8ec61abef2816..111dbf3810b448a4e9b0d1c244cf33de5eb2423e 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -3405,6 +3405,19 @@ class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
   let DecoderMethod = "DecodeSignedLdStInstruction";
 }
 
+// Armv8.4 LDAPR & STLR with Immediate Offset instruction
+multiclass BaseLoadStoreUnscaleV84<string asm, bits<2> sz, bits<2> opc,
+                                   RegisterOperand regtype > {
+  def i : BaseLoadStoreUnscale<sz, 0, opc, (outs regtype:$Rt),
+                               (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
+          Sched<[WriteST]> {
+    let Inst{29} = 0;
+    let Inst{24} = 1;
+  }
+  def : InstAlias<asm # "\t$Rt, [$Rn]",
+                  (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
+}
+
 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
                    string asm, list<dag> pattern> {
   let AddedComplexity = 1 in // try this before LoadUI

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index bc92fa426309e26faddc5979707c7c333a04faa2..0d008beacd6c941ef2a312962ef77c3a96b9db1a 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2430,6 +2430,23 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
                          [(truncstorei8 GPR32z:$Rt,
                                   (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
 
+// Armv8.4 LDAPR & STLR with Immediate Offset instruction
+let Predicates = [HasV8_4a] in {
+defm STLURB     : BaseLoadStoreUnscaleV84<"stlurb",   0b00, 0b00, GPR32>;
+defm STLURH     : BaseLoadStoreUnscaleV84<"stlurh",   0b01, 0b00, GPR32>;
+defm STLUR      : BaseLoadStoreUnscaleV84<"stlur",    0b10, 0b00, GPR32>;
+defm STLUR64    : BaseLoadStoreUnscaleV84<"stlur",    0b11, 0b00, GPR64>;
+defm LDAPURB    : BaseLoadStoreUnscaleV84<"ldapurb",  0b00, 0b01, GPR32>;
+defm LDAPURSB   : BaseLoadStoreUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
+defm LDAPURSB64 : BaseLoadStoreUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;
+defm LDAPURH    : BaseLoadStoreUnscaleV84<"ldapurh",  0b01, 0b01, GPR32>;
+defm LDAPURSH   : BaseLoadStoreUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
+defm LDAPURSH64 : BaseLoadStoreUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;
+defm LDAPUR     : BaseLoadStoreUnscaleV84<"ldapur",   0b10, 0b01, GPR32>;
+defm LDAPURSW   : BaseLoadStoreUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;
+defm LDAPUR64   : BaseLoadStoreUnscaleV84<"ldapur",   0b11, 0b01, GPR64>;
+}
+
 // Match all store 64 bits width whose type is compatible with FPR64
 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
           (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;

diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 5089f1e6e8ef20ad49d4acdb2e7a6362615daa22..ff3e0ca8dc6dde19339c771aceb7cfbf2fbab834 100644 (file)
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1183,6 +1183,14 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
   case AArch64::LDRHHpost:
   case AArch64::STRWpost:
   case AArch64::LDRWpost:
+  case AArch64::STLURBi:
+  case AArch64::STLURHi:
+  case AArch64::STLURi:
+  case AArch64::LDAPURBi:
+  case AArch64::LDAPURSBi:
+  case AArch64::LDAPURHi:
+  case AArch64::LDAPURSHi:
+  case AArch64::LDAPURi:
     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   case AArch64::LDURSBXi:
@@ -1205,6 +1213,11 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
   case AArch64::STRXpost:
   case AArch64::LDRSWpost:
   case AArch64::LDRXpost:
+  case AArch64::LDAPURSWi:
+  case AArch64::LDAPURSH64i:
+  case AArch64::LDAPURSB64i:
+  case AArch64::STLUR64i:
+  case AArch64::LDAPUR64i:
     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   case AArch64::LDURQi: