[ARM] MVE: allow soft-float ABI to pass vector types.

Passing a vector type over the soft-float ABI involves it being split
into four GPRs, so the first thing that has to happen at the start of
the function is to recombine those into a vector register. The ABI
types all vectors as v2f64, so we need to support BUILD_VECTOR for
that type, which I do in this patch by allowing it to be expanded in
terms of INSERT_VECTOR_ELT, and writing an ISel pattern for that in
turn. Similarly, I provide a rule for EXTRACT_VECTOR_ELT so that a
returned vector can be marshalled back into GPRs.

While I'm here, I've also added ISD::UNDEF to the list of operations
we turn back on in `setAllExpand`, because I noticed that otherwise it
gets expanded into a BUILD_VECTOR with explicit zero inputs, leading
to pointless machine instructions to zero out a vector register that's
about to have every lane overwritten of in any case.

Reviewers: dmgreen, ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63937

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364910 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 36c783c2e650206eab6fb7f7dc40e62895e6df0d..efa97b4200fb7146dd6b39422a81652cd0959c19 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -231,6 +231,7 @@ void ARMTargetLowering::setAllExpand(MVT VT) {
   setOperationAction(ISD::BITCAST, VT, Legal);
   setOperationAction(ISD::LOAD, VT, Legal);
   setOperationAction(ISD::STORE, VT, Legal);
+  setOperationAction(ISD::UNDEF, VT, Legal);
 }
 
 void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
@@ -266,8 +267,10 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
     // These are legal or custom whether we have MVE.fp or not
     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+    setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
 
     if (HasMVEFP) {
@@ -293,6 +296,9 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
   for (auto VT : LongTypes) {
     addRegisterClass(VT, &ARM::QPRRegClass);
     setAllExpand(VT);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
+    setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
   }
 
   // It is legal to extload from v4i8 to v4i16 or v4i32.
@@ -6747,7 +6753,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
   // Vectors with 32- or 64-bit elements can be built by directly assigning
   // the subregisters.  Lower it to an ARMISD::BUILD_VECTOR so the operands
   // will be legalized.
-  if (ST->hasNEON() && EltSize >= 32) {
+  if (EltSize >= 32) {
     // Do the expansion with floating-point types, since that is what the VFP
     // registers are defined to use, and since i64 is not legal.
     EVT EltVT = EVT::getFloatingPointVT(EltSize);
@@ -7344,12 +7350,40 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
   return SDValue();
 }
 
-static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
+SDValue ARMTargetLowering::
+LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
   // INSERT_VECTOR_ELT is legal only for immediate indexes.
   SDValue Lane = Op.getOperand(2);
   if (!isa<ConstantSDNode>(Lane))
     return SDValue();
 
+  SDValue Elt = Op.getOperand(1);
+  EVT EltVT = Elt.getValueType();
+  if (getTypeAction(*DAG.getContext(), EltVT) ==
+      TargetLowering::TypePromoteFloat) {
+    // INSERT_VECTOR_ELT doesn't want f16 operands promoting to f32,
+    // but the type system will try to do that if we don't intervene.
+    // Reinterpret any such vector-element insertion as one with the
+    // corresponding integer types.
+
+    SDLoc dl(Op);
+
+    EVT IEltVT = MVT::getIntegerVT(EltVT.getScalarSizeInBits());
+    assert(getTypeAction(*DAG.getContext(), IEltVT) !=
+           TargetLowering::TypePromoteFloat);
+
+    SDValue VecIn = Op.getOperand(0);
+    EVT VecVT = VecIn.getValueType();
+    EVT IVecVT = EVT::getVectorVT(*DAG.getContext(), IEltVT,
+                                  VecVT.getVectorNumElements());
+
+    SDValue IElt = DAG.getNode(ISD::BITCAST, dl, IEltVT, Elt);
+    SDValue IVecIn = DAG.getNode(ISD::BITCAST, dl, IVecVT, VecIn);
+    SDValue IVecOut = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, IVecVT,
+                                  IVecIn, IElt, Lane);
+    return DAG.getNode(ISD::BITCAST, dl, VecVT, IVecOut);
+  }
+
   return Op;
 }
 

diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index ca8b042c56be8c34b680bf15a0efcd39bf079ad9..d188ad2facb6e7371f92ec9ffe2ccc087b320f73 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -693,6 +693,7 @@ class VectorType;
                             const ARMSubtarget *ST) const;
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
                               const ARMSubtarget *ST) const;
+    SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;

diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td
index 5282e62e383535c513ad8fe3daec43cc899618f8..9073b49acb4452ad68b7618e3fe055f3dfc42efe 100644 (file)
--- a/lib/Target/ARM/ARMInstrMVE.td
+++ b/lib/Target/ARM/ARMInstrMVE.td
@@ -1719,6 +1719,11 @@ def MVE_VMOV_from_lane_u8  : MVE_VMOV_lane_8 < "u8", 0b1, MVE_VMOV_from_lane>;
 def MVE_VMOV_to_lane_8     : MVE_VMOV_lane_8 <  "8", 0b0, MVE_VMOV_to_lane>;
 
 let Predicates = [HasMVEInt] in {
+  def : Pat<(extractelt (v2f64 MQPR:$src), imm:$lane),
+            (f64 (EXTRACT_SUBREG MQPR:$src, (DSubReg_f64_reg imm:$lane)))>;
+  def : Pat<(insertelt (v2f64 MQPR:$src1), DPR:$src2, imm:$lane),
+            (INSERT_SUBREG (v2f64 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), DPR:$src2, (DSubReg_f64_reg imm:$lane))>;
+
   def : Pat<(extractelt (v4i32 MQPR:$src), imm:$lane),
             (COPY_TO_REGCLASS
               (i32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), rGPR)>;

diff --git a/test/CodeGen/Thumb2/mve-div-expand.ll b/test/CodeGen/Thumb2/mve-div-expand.ll
index 7b3b8135c4fbadb5693160291c7ece617561c6f2..89361f0693c70ffb9da4cc9c06b755eacb32bef0 100644 (file)
--- a/test/CodeGen/Thumb2/mve-div-expand.ll
+++ b/test/CodeGen/Thumb2/mve-div-expand.ll
@@ -738,114 +738,57 @@ entry:
 
 
 define arm_aapcs_vfpcc <4 x float> @fdiv_f32(<4 x float> %in1, <4 x float> %in2) {
-; CHECK-MVE-LABEL: fdiv_f32:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    vdiv.f32 s8, s0, s4
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vdiv.f32 s10, s1, s5
-; CHECK-MVE-NEXT:    vdiv.f32 s12, s2, s6
-; CHECK-MVE-NEXT:    vdiv.f32 s4, s3, s7
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s8
-; CHECK-MVE-NEXT:    vmov.f32 s1, s10
-; CHECK-MVE-NEXT:    vmov.f32 s2, s12
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-MVEFP-LABEL: fdiv_f32:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    vmov q2, q0
-; CHECK-MVEFP-NEXT:    vdiv.f32 s0, s8, s4
-; CHECK-MVEFP-NEXT:    vdiv.f32 s1, s9, s5
-; CHECK-MVEFP-NEXT:    vdiv.f32 s2, s10, s6
-; CHECK-MVEFP-NEXT:    vdiv.f32 s3, s11, s7
-; CHECK-MVEFP-NEXT:    bx lr
+; CHECK-LABEL: fdiv_f32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vdiv.f32 s11, s3, s7
+; CHECK-NEXT:    vdiv.f32 s10, s2, s6
+; CHECK-NEXT:    vdiv.f32 s9, s1, s5
+; CHECK-NEXT:    vdiv.f32 s8, s0, s4
+; CHECK-NEXT:    vmov q0, q2
+; CHECK-NEXT:    bx lr
 entry:
   %out = fdiv <4 x float> %in1, %in2
   ret <4 x float> %out
 }
 
 define arm_aapcs_vfpcc <4 x float> @frem_f32(<4 x float> %in1, <4 x float> %in2) {
-; CHECK-MVE-LABEL: frem_f32:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r6, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r6, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vstr s3, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r4, [sp, #24]
-; CHECK-MVE-NEXT:    vstr s1, [sp, #8]
-; CHECK-MVE-NEXT:    vstr s5, [sp, #12]
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    vstr s4, [sp, #4]
-; CHECK-MVE-NEXT:    vstr s7, [sp, #28]
-; CHECK-MVE-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVE-NEXT:    vstr s6, [sp, #20]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    mov r5, r0
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    ldrd r2, r1, [sp, #16]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    ldr r6, [sp, #28]
-; CHECK-MVE-NEXT:    vmov s18, r5
-; CHECK-MVE-NEXT:    mov r0, r2
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r4
-; CHECK-MVE-NEXT:    mov r1, r6
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r6, pc}
-;
-; CHECK-MVEFP-LABEL: frem_f32:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r6, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r6, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vstr s3, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r4, [sp, #24]
-; CHECK-MVEFP-NEXT:    vstr s1, [sp, #8]
-; CHECK-MVEFP-NEXT:    vstr s5, [sp, #12]
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    vstr s4, [sp, #4]
-; CHECK-MVEFP-NEXT:    vstr s7, [sp, #28]
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVEFP-NEXT:    vstr s6, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    mov r5, r0
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    ldrd r2, r1, [sp, #16]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    ldr r6, [sp, #28]
-; CHECK-MVEFP-NEXT:    vmov s17, r5
-; CHECK-MVEFP-NEXT:    mov r0, r2
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r4
-; CHECK-MVEFP-NEXT:    mov r1, r6
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r6, pc}
+; CHECK-LABEL: frem_f32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r6, lr}
+; CHECK-NEXT:    push {r4, r5, r6, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r4, [sp]
+; CHECK-NEXT:    vstr s2, [sp, #16]
+; CHECK-NEXT:    vstr s6, [sp, #20]
+; CHECK-NEXT:    vstr s3, [sp, #24]
+; CHECK-NEXT:    vstr s7, [sp, #28]
+; CHECK-NEXT:    vstr s4, [sp, #4]
+; CHECK-NEXT:    vstr s1, [sp, #8]
+; CHECK-NEXT:    vstr s5, [sp, #12]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #16]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    mov r5, r0
+; CHECK-NEXT:    ldrd r0, r1, [sp, #24]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    ldr r1, [sp, #12]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    ldrd r6, r2, [sp, #4]
+; CHECK-NEXT:    vmov s18, r5
+; CHECK-NEXT:    mov r0, r2
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r4
+; CHECK-NEXT:    mov r1, r6
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %out = frem <4 x float> %in1, %in2
   ret <4 x float> %out
@@ -853,390 +796,198 @@ entry:
 
 
 define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) {
-; CHECK-MVE-LABEL: fdiv_f16:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-MVE-NEXT:    vmov.u16 r1, q0[0]
-; CHECK-MVE-NEXT:    vmov s10, r1
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[1]
-; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    movs r2, #0
-; CHECK-MVE-NEXT:    vdiv.f16 s8, s10, s8
-; CHECK-MVE-NEXT:    vmov r0, s8
-; CHECK-MVE-NEXT:    vmov s8, r1
-; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
-; CHECK-MVE-NEXT:    vmov s10, r1
-; CHECK-MVE-NEXT:    vdiv.f16 s8, s10, s8
-; CHECK-MVE-NEXT:    vmov r1, s8
-; CHECK-MVE-NEXT:    vdup.16 q2, r2
-; CHECK-MVE-NEXT:    vmov.16 q2[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[2]
-; CHECK-MVE-NEXT:    vmov s12, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
-; CHECK-MVE-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVE-NEXT:    vmov r0, s12
-; CHECK-MVE-NEXT:    vmov.16 q2[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[3]
-; CHECK-MVE-NEXT:    vmov s12, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVE-NEXT:    vmov r0, s12
-; CHECK-MVE-NEXT:    vmov.16 q2[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[4]
-; CHECK-MVE-NEXT:    vmov s12, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVE-NEXT:    vmov r0, s12
-; CHECK-MVE-NEXT:    vmov.16 q2[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[5]
-; CHECK-MVE-NEXT:    vmov s12, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVE-NEXT:    vmov r0, s12
-; CHECK-MVE-NEXT:    vmov.16 q2[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[6]
-; CHECK-MVE-NEXT:    vmov s12, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVE-NEXT:    vmov r0, s12
-; CHECK-MVE-NEXT:    vmov.16 q2[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[7]
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vdiv.f16 s0, s0, s4
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q2[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q2
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-MVEFP-LABEL: fdiv_f16:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-MVEFP-NEXT:    vmov.u16 r1, q1[1]
-; CHECK-MVEFP-NEXT:    vmov s8, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVEFP-NEXT:    vmov s10, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r2, q0[1]
-; CHECK-MVEFP-NEXT:    vdiv.f16 s8, s10, s8
-; CHECK-MVEFP-NEXT:    vmov s10, r2
-; CHECK-MVEFP-NEXT:    vmov r0, s8
-; CHECK-MVEFP-NEXT:    vmov s8, r1
-; CHECK-MVEFP-NEXT:    vdiv.f16 s8, s10, s8
-; CHECK-MVEFP-NEXT:    vmov r1, s8
-; CHECK-MVEFP-NEXT:    vmov.16 q2[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[2]
-; CHECK-MVEFP-NEXT:    vmov.16 q2[1], r1
-; CHECK-MVEFP-NEXT:    vmov s12, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVEFP-NEXT:    vmov s14, r0
-; CHECK-MVEFP-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVEFP-NEXT:    vmov r0, s12
-; CHECK-MVEFP-NEXT:    vmov.16 q2[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[3]
-; CHECK-MVEFP-NEXT:    vmov s12, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVEFP-NEXT:    vmov s14, r0
-; CHECK-MVEFP-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVEFP-NEXT:    vmov r0, s12
-; CHECK-MVEFP-NEXT:    vmov.16 q2[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[4]
-; CHECK-MVEFP-NEXT:    vmov s12, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVEFP-NEXT:    vmov s14, r0
-; CHECK-MVEFP-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVEFP-NEXT:    vmov r0, s12
-; CHECK-MVEFP-NEXT:    vmov.16 q2[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[5]
-; CHECK-MVEFP-NEXT:    vmov s12, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVEFP-NEXT:    vmov s14, r0
-; CHECK-MVEFP-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVEFP-NEXT:    vmov r0, s12
-; CHECK-MVEFP-NEXT:    vmov.16 q2[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[6]
-; CHECK-MVEFP-NEXT:    vmov s12, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVEFP-NEXT:    vmov s14, r0
-; CHECK-MVEFP-NEXT:    vdiv.f16 s12, s14, s12
-; CHECK-MVEFP-NEXT:    vmov r0, s12
-; CHECK-MVEFP-NEXT:    vmov.16 q2[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[7]
-; CHECK-MVEFP-NEXT:    vmov s4, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vdiv.f16 s0, s0, s4
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q2[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q2
-; CHECK-MVEFP-NEXT:    bx lr
+; CHECK-LABEL: fdiv_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u16 r0, q1[0]
+; CHECK-NEXT:    vmov.u16 r1, q1[1]
+; CHECK-NEXT:    vmov s8, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[0]
+; CHECK-NEXT:    vmov s10, r0
+; CHECK-NEXT:    vmov.u16 r2, q0[1]
+; CHECK-NEXT:    vdiv.f16 s8, s10, s8
+; CHECK-NEXT:    vmov s10, r2
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov s8, r1
+; CHECK-NEXT:    vdiv.f16 s8, s10, s8
+; CHECK-NEXT:    vmov r1, s8
+; CHECK-NEXT:    vmov.16 q2[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q1[2]
+; CHECK-NEXT:    vmov.16 q2[1], r1
+; CHECK-NEXT:    vmov s12, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-NEXT:    vmov s14, r0
+; CHECK-NEXT:    vdiv.f16 s12, s14, s12
+; CHECK-NEXT:    vmov r0, s12
+; CHECK-NEXT:    vmov.16 q2[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q1[3]
+; CHECK-NEXT:    vmov s12, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[3]
+; CHECK-NEXT:    vmov s14, r0
+; CHECK-NEXT:    vdiv.f16 s12, s14, s12
+; CHECK-NEXT:    vmov r0, s12
+; CHECK-NEXT:    vmov.16 q2[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q1[4]
+; CHECK-NEXT:    vmov s12, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[4]
+; CHECK-NEXT:    vmov s14, r0
+; CHECK-NEXT:    vdiv.f16 s12, s14, s12
+; CHECK-NEXT:    vmov r0, s12
+; CHECK-NEXT:    vmov.16 q2[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q1[5]
+; CHECK-NEXT:    vmov s12, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[5]
+; CHECK-NEXT:    vmov s14, r0
+; CHECK-NEXT:    vdiv.f16 s12, s14, s12
+; CHECK-NEXT:    vmov r0, s12
+; CHECK-NEXT:    vmov.16 q2[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q1[6]
+; CHECK-NEXT:    vmov s12, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[6]
+; CHECK-NEXT:    vmov s14, r0
+; CHECK-NEXT:    vdiv.f16 s12, s14, s12
+; CHECK-NEXT:    vmov r0, s12
+; CHECK-NEXT:    vmov.16 q2[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q1[7]
+; CHECK-NEXT:    vmov s4, r0
+; CHECK-NEXT:    vmov.u16 r0, q0[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vdiv.f16 s0, s0, s4
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q2[7], r0
+; CHECK-NEXT:    vmov q0, q2
+; CHECK-NEXT:    bx lr
 entry:
   %out = fdiv <8 x half> %in1, %in2
   ret <8 x half> %out
 }
 
 define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
-; CHECK-MVE-LABEL: frem_f16:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT:    .pad #64
-; CHECK-MVE-NEXT:    sub sp, #64
-; CHECK-MVE-NEXT:    vmov q5, q1
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #56]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #60]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #56]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[1]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[1]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #48]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #52]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #48]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vdup.16 q6, r1
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[0], r4
-; CHECK-MVE-NEXT:    vmov.16 q6[1], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #40]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #44]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #40]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #32]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #36]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #32]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #24]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #24]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #16]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #8]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVE-NEXT:    bl fmodf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q6
-; CHECK-MVE-NEXT:    add sp, #64
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: frem_f16:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
-; CHECK-MVEFP-NEXT:    .pad #64
-; CHECK-MVEFP-NEXT:    sub sp, #64
-; CHECK-MVEFP-NEXT:    vmov q5, q1
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #56]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #60]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #56]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[1]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[1]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #48]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #52]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #48]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[0], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[1], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #40]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #44]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #40]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #32]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #36]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #32]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #24]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #8]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVEFP-NEXT:    bl fmodf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q6
-; CHECK-MVEFP-NEXT:    add sp, #64
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: frem_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT:    .pad #64
+; CHECK-NEXT:    sub sp, #64
+; CHECK-NEXT:    vmov q5, q1
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov.u16 r0, q1[0]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #56]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #60]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #56]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q5[1]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[1]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #48]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #52]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #48]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q6[0], r4
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[1], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #40]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #44]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #40]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #32]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #36]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #32]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #24]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #24]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #16]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #16]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #8]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #8]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldrd r0, r1, [sp]
+; CHECK-NEXT:    bl fmodf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[7], r0
+; CHECK-NEXT:    vmov q0, q6
+; CHECK-NEXT:    add sp, #64
+; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %out = frem <8 x half> %in1, %in2
   ret <8 x half> %out

diff --git a/test/CodeGen/Thumb2/mve-fmath.ll b/test/CodeGen/Thumb2/mve-fmath.ll
index d4bd3901bdb0d1e0248128f2e3a519391f4de159..588904379e137c55f2e25b6a8e45ef9706c7c8c1 100644 (file)
--- a/test/CodeGen/Thumb2/mve-fmath.ll
+++ b/test/CodeGen/Thumb2/mve-fmath.ll
@@ -3,2299 +3,1163 @@
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
 
 define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: sqrt_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    vsqrt.f32 s4, s0
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vsqrt.f32 s6, s1
-; CHECK-MVE-NEXT:    vsqrt.f32 s8, s2
-; CHECK-MVE-NEXT:    vsqrt.f32 s10, s3
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s4
-; CHECK-MVE-NEXT:    vmov.f32 s1, s6
-; CHECK-MVE-NEXT:    vmov.f32 s2, s8
-; CHECK-MVE-NEXT:    vmov.f32 s3, s10
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-MVEFP-LABEL: sqrt_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    vsqrt.f32 s4, s0
-; CHECK-MVEFP-NEXT:    vsqrt.f32 s5, s1
-; CHECK-MVEFP-NEXT:    vsqrt.f32 s6, s2
-; CHECK-MVEFP-NEXT:    vsqrt.f32 s7, s3
-; CHECK-MVEFP-NEXT:    vmov q0, q1
-; CHECK-MVEFP-NEXT:    bx lr
+; CHECK-LABEL: sqrt_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsqrt.f32 s7, s3
+; CHECK-NEXT:    vsqrt.f32 s6, s2
+; CHECK-NEXT:    vsqrt.f32 s5, s1
+; CHECK-NEXT:    vsqrt.f32 s4, s0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
 entry:
   %0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: sqrt_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    movs r2, #0
-; CHECK-MVE-NEXT:    vsqrt.f16 s4, s4
-; CHECK-MVE-NEXT:    vmov r0, s4
-; CHECK-MVE-NEXT:    vmov s4, r1
-; CHECK-MVE-NEXT:    vsqrt.f16 s4, s4
-; CHECK-MVE-NEXT:    vmov r1, s4
-; CHECK-MVE-NEXT:    vdup.16 q1, r2
-; CHECK-MVE-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVE-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVE-NEXT:    vmov r0, s8
-; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVE-NEXT:    vmov r0, s8
-; CHECK-MVE-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVE-NEXT:    vmov r0, s8
-; CHECK-MVE-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVE-NEXT:    vmov r0, s8
-; CHECK-MVE-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVE-NEXT:    vmov r0, s8
-; CHECK-MVE-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vsqrt.f16 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q1
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-MVEFP-LABEL: sqrt_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVEFP-NEXT:    vmov.u16 r1, q0[1]
-; CHECK-MVEFP-NEXT:    vmov s4, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s4, s4
-; CHECK-MVEFP-NEXT:    vmov r0, s4
-; CHECK-MVEFP-NEXT:    vmov s4, r1
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s4, s4
-; CHECK-MVEFP-NEXT:    vmov r1, s4
-; CHECK-MVEFP-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVEFP-NEXT:    vmov s8, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVEFP-NEXT:    vmov r0, s8
-; CHECK-MVEFP-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVEFP-NEXT:    vmov s8, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVEFP-NEXT:    vmov r0, s8
-; CHECK-MVEFP-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVEFP-NEXT:    vmov s8, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVEFP-NEXT:    vmov r0, s8
-; CHECK-MVEFP-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVEFP-NEXT:    vmov s8, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVEFP-NEXT:    vmov r0, s8
-; CHECK-MVEFP-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVEFP-NEXT:    vmov s8, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s8, s8
-; CHECK-MVEFP-NEXT:    vmov r0, s8
-; CHECK-MVEFP-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vsqrt.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q1[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q1
-; CHECK-MVEFP-NEXT:    bx lr
+; CHECK-LABEL: sqrt_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u16 r0, q0[0]
+; CHECK-NEXT:    vmov.u16 r1, q0[1]
+; CHECK-NEXT:    vmov s4, r0
+; CHECK-NEXT:    vsqrt.f16 s4, s4
+; CHECK-NEXT:    vmov r0, s4
+; CHECK-NEXT:    vmov s4, r1
+; CHECK-NEXT:    vsqrt.f16 s4, s4
+; CHECK-NEXT:    vmov r1, s4
+; CHECK-NEXT:    vmov.16 q1[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-NEXT:    vmov.16 q1[1], r1
+; CHECK-NEXT:    vmov s8, r0
+; CHECK-NEXT:    vsqrt.f16 s8, s8
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov.16 q1[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[3]
+; CHECK-NEXT:    vmov s8, r0
+; CHECK-NEXT:    vsqrt.f16 s8, s8
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov.16 q1[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[4]
+; CHECK-NEXT:    vmov s8, r0
+; CHECK-NEXT:    vsqrt.f16 s8, s8
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov.16 q1[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[5]
+; CHECK-NEXT:    vmov s8, r0
+; CHECK-NEXT:    vsqrt.f16 s8, s8
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov.16 q1[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[6]
+; CHECK-NEXT:    vmov s8, r0
+; CHECK-NEXT:    vsqrt.f16 s8, s8
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov.16 q1[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vsqrt.f16 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q1[7], r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
 entry:
   %0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @cos_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: cos_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: cos_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: cos_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.cos.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: cos_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl cosf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: cos_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl cosf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: cos_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl cosf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @sin_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: sin_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: sin_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: sin_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.sin.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: sin_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl sinf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: sin_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl sinf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: sin_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @exp_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: exp_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: exp_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: exp_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.exp.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: exp_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl expf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: exp_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl expf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: exp_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl expf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @exp2_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: exp2_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: exp2_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: exp2_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.exp2.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: exp2_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl exp2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: exp2_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl exp2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: exp2_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl exp2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @log_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: log_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: log_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: log_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.log.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: log_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl logf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: log_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl logf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: log_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl logf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @log2_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: log2_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: log2_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: log2_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.log2.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: log2_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl log2f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: log2_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl log2f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: log2_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl log2f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @log10_float32_t(<4 x float> %src) {
-; CHECK-MVE-LABEL: log10_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #16
-; CHECK-MVE-NEXT:    sub sp, #16
-; CHECK-MVE-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    mov r4, r0
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    vmov s18, r4
-; CHECK-MVE-NEXT:    mov r0, r1
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r5
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #16
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r7, pc}
-;
-; CHECK-MVEFP-LABEL: log10_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r7, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #16
-; CHECK-MVEFP-NEXT:    sub sp, #16
-; CHECK-MVEFP-NEXT:    vstmia sp, {s0, s1, s2, s3}
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    mov r4, r0
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    ldrd r1, r5, [sp, #8]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    vmov s17, r4
-; CHECK-MVEFP-NEXT:    mov r0, r1
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r5
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #16
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LABEL: log10_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r7, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    vstmia sp, {s0, s1, s2, s3}
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    ldrd r5, r1, [sp]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    vmov s18, r4
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r5
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %0 = call fast <4 x float> @llvm.log10.v4f32(<4 x float> %src)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {
-; CHECK-MVE-LABEL: log10_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vdup.16 q5, r1
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    ldr r0, [sp]
-; CHECK-MVE-NEXT:    bl log10f
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q5
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: log10_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #28]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[1], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #20]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #16]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #12]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #8]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp, #4]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    ldr r0, [sp]
-; CHECK-MVEFP-NEXT:    bl log10f
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q5[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q5
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: log10_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #24]
+; CHECK-NEXT:    ldr r0, [sp, #24]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldr r0, [sp, #28]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q5[1], r4
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldr r0, [sp, #20]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #16]
+; CHECK-NEXT:    ldr r0, [sp, #16]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldr r0, [sp, #12]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #8]
+; CHECK-NEXT:    ldr r0, [sp, #8]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldr r0, [sp, #4]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r0, [sp]
+; CHECK-NEXT:    bl log10f
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q5[7], r0
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9, d10, d11}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)
   ret <8 x half> %0
 }
 
 define arm_aapcs_vfpcc <4 x float> @pow_float32_t(<4 x float> %src1, <4 x float> %src2) {
-; CHECK-MVE-LABEL: pow_float32_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, r5, r6, lr}
-; CHECK-MVE-NEXT:    push {r4, r5, r6, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10}
-; CHECK-MVE-NEXT:    .pad #32
-; CHECK-MVE-NEXT:    sub sp, #32
-; CHECK-MVE-NEXT:    vstr s3, [sp, #24]
-; CHECK-MVE-NEXT:    ldr r4, [sp, #24]
-; CHECK-MVE-NEXT:    vstr s1, [sp, #8]
-; CHECK-MVE-NEXT:    vstr s5, [sp, #12]
-; CHECK-MVE-NEXT:    vstr s0, [sp]
-; CHECK-MVE-NEXT:    vstr s4, [sp, #4]
-; CHECK-MVE-NEXT:    vstr s7, [sp, #28]
-; CHECK-MVE-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVE-NEXT:    vstr s6, [sp, #20]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    mov r5, r0
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    ldrd r2, r1, [sp, #16]
-; CHECK-MVE-NEXT:    vmov s16, r0
-; CHECK-MVE-NEXT:    ldr r6, [sp, #28]
-; CHECK-MVE-NEXT:    vmov s18, r5
-; CHECK-MVE-NEXT:    mov r0, r2
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s20, r0
-; CHECK-MVE-NEXT:    mov r0, r4
-; CHECK-MVE-NEXT:    mov r1, r6
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    vdup.32 q0, r1
-; CHECK-MVE-NEXT:    vmov.f32 s0, s16
-; CHECK-MVE-NEXT:    vmov.f32 s1, s18
-; CHECK-MVE-NEXT:    vmov.f32 s2, s20
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
-; CHECK-MVE-NEXT:    add sp, #32
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10}
-; CHECK-MVE-NEXT:    pop {r4, r5, r6, pc}
-;
-; CHECK-MVEFP-LABEL: pow_float32_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, r5, r6, lr}
-; CHECK-MVEFP-NEXT:    push {r4, r5, r6, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9}
-; CHECK-MVEFP-NEXT:    .pad #32
-; CHECK-MVEFP-NEXT:    sub sp, #32
-; CHECK-MVEFP-NEXT:    vstr s3, [sp, #24]
-; CHECK-MVEFP-NEXT:    ldr r4, [sp, #24]
-; CHECK-MVEFP-NEXT:    vstr s1, [sp, #8]
-; CHECK-MVEFP-NEXT:    vstr s5, [sp, #12]
-; CHECK-MVEFP-NEXT:    vstr s0, [sp]
-; CHECK-MVEFP-NEXT:    vstr s4, [sp, #4]
-; CHECK-MVEFP-NEXT:    vstr s7, [sp, #28]
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVEFP-NEXT:    vstr s6, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    mov r5, r0
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    ldrd r2, r1, [sp, #16]
-; CHECK-MVEFP-NEXT:    vmov s16, r0
-; CHECK-MVEFP-NEXT:    ldr r6, [sp, #28]
-; CHECK-MVEFP-NEXT:    vmov s17, r5
-; CHECK-MVEFP-NEXT:    mov r0, r2
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s18, r0
-; CHECK-MVEFP-NEXT:    mov r0, r4
-; CHECK-MVEFP-NEXT:    mov r1, r6
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s19, r0
-; CHECK-MVEFP-NEXT:    vmov q0, q4
-; CHECK-MVEFP-NEXT:    add sp, #32
-; CHECK-MVEFP-NEXT:    vpop {d8, d9}
-; CHECK-MVEFP-NEXT:    pop {r4, r5, r6, pc}
+; CHECK-LABEL: pow_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r6, lr}
+; CHECK-NEXT:    push {r4, r5, r6, lr}
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
+; CHECK-NEXT:    .pad #32
+; CHECK-NEXT:    sub sp, #32
+; CHECK-NEXT:    vstr s0, [sp]
+; CHECK-NEXT:    ldr r4, [sp]
+; CHECK-NEXT:    vstr s2, [sp, #16]
+; CHECK-NEXT:    vstr s6, [sp, #20]
+; CHECK-NEXT:    vstr s3, [sp, #24]
+; CHECK-NEXT:    vstr s7, [sp, #28]
+; CHECK-NEXT:    vstr s4, [sp, #4]
+; CHECK-NEXT:    vstr s1, [sp, #8]
+; CHECK-NEXT:    vstr s5, [sp, #12]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #16]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    mov r5, r0
+; CHECK-NEXT:    ldrd r0, r1, [sp, #24]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    ldr r1, [sp, #12]
+; CHECK-NEXT:    vmov s19, r0
+; CHECK-NEXT:    ldrd r6, r2, [sp, #4]
+; CHECK-NEXT:    vmov s18, r5
+; CHECK-NEXT:    mov r0, r2
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s17, r0
+; CHECK-NEXT:    mov r0, r4
+; CHECK-NEXT:    mov r1, r6
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s16, r0
+; CHECK-NEXT:    vmov q0, q4
+; CHECK-NEXT:    add sp, #32
+; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %0 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %src1, <4 x float> %src2)
   ret <4 x float> %0
 }
 
 define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {
-; CHECK-MVE-LABEL: pow_float16_t:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    .save {r4, lr}
-; CHECK-MVE-NEXT:    push {r4, lr}
-; CHECK-MVE-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT:    .pad #64
-; CHECK-MVE-NEXT:    sub sp, #64
-; CHECK-MVE-NEXT:    vmov q5, q1
-; CHECK-MVE-NEXT:    vmov q4, q0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #56]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #60]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #56]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[1]
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r4, s0
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[1]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #48]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #52]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #48]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    movs r1, #0
-; CHECK-MVE-NEXT:    vdup.16 q6, r1
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[0], r4
-; CHECK-MVE-NEXT:    vmov.16 q6[1], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[2]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #40]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #44]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #40]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[3]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #32]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #36]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #32]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[4]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #24]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #24]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[5]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #16]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[6]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp, #8]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q5[7]
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVE-NEXT:    vmov s2, r0
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT:    vstr s2, [sp]
-; CHECK-MVE-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVE-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVE-NEXT:    bl powf
-; CHECK-MVE-NEXT:    vmov s0, r0
-; CHECK-MVE-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
-; CHECK-MVE-NEXT:    vmov.16 q6[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q6
-; CHECK-MVE-NEXT:    add sp, #64
-; CHECK-MVE-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT:    pop {r4, pc}
-;
-; CHECK-MVEFP-LABEL: pow_float16_t:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    .save {r4, lr}
-; CHECK-MVEFP-NEXT:    push {r4, lr}
-; CHECK-MVEFP-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
-; CHECK-MVEFP-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
-; CHECK-MVEFP-NEXT:    .pad #64
-; CHECK-MVEFP-NEXT:    sub sp, #64
-; CHECK-MVEFP-NEXT:    vmov q5, q1
-; CHECK-MVEFP-NEXT:    vmov q4, q0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[0]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #56]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #60]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #56]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[1]
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r4, s0
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[1]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #48]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #52]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #48]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[0], r4
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[1], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[2]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[2]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #40]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #44]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #40]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[3]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[3]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #32]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #36]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #32]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[4]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[4]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #24]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #28]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #24]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[5]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[5]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #16]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #20]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #16]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[6]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[6]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp, #8]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #12]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp, #8]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q5[7]
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q4[7]
-; CHECK-MVEFP-NEXT:    vmov s2, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-MVEFP-NEXT:    vstr s2, [sp]
-; CHECK-MVEFP-NEXT:    vcvtb.f32.f16 s0, s0
-; CHECK-MVEFP-NEXT:    vstr s0, [sp, #4]
-; CHECK-MVEFP-NEXT:    ldrd r0, r1, [sp]
-; CHECK-MVEFP-NEXT:    bl powf
-; CHECK-MVEFP-NEXT:    vmov s0, r0
-; CHECK-MVEFP-NEXT:    vcvtb.f16.f32 s0, s0
-; CHECK-MVEFP-NEXT:    vmov r0, s0
-; CHECK-MVEFP-NEXT:    vmov.16 q6[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q6
-; CHECK-MVEFP-NEXT:    add sp, #64
-; CHECK-MVEFP-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-MVEFP-NEXT:    pop {r4, pc}
+; CHECK-LABEL: pow_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT:    .pad #64
+; CHECK-NEXT:    sub sp, #64
+; CHECK-NEXT:    vmov q5, q1
+; CHECK-NEXT:    vmov q4, q0
+; CHECK-NEXT:    vmov.u16 r0, q1[0]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[0]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #56]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #60]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #56]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q5[1]
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r4, s0
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[1]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #48]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #52]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #48]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.16 q6[0], r4
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[1], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[2]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[2]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #40]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #44]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #40]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[3]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #32]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #36]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #32]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[4]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[4]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #24]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #28]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #24]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[5]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #16]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #20]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #16]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[6]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[6]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp, #8]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #12]
+; CHECK-NEXT:    ldrd r0, r1, [sp, #8]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q5[7]
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.u16 r0, q4[7]
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vstr s2, [sp]
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-NEXT:    vstr s0, [sp, #4]
+; CHECK-NEXT:    ldrd r0, r1, [sp]
+; CHECK-NEXT:    bl powf
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vmov.16 q6[7], r0
+; CHECK-NEXT:    vmov q0, q6
+; CHECK-NEXT:    add sp, #64
+; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)
   ret <8 x half> %0

diff --git a/test/CodeGen/Thumb2/mve-fp-negabs.ll b/test/CodeGen/Thumb2/mve-fp-negabs.ll
index e323a10657bbe8963eee6d79202be0cfcb0c3c6b..2489646ad6d622384b958c9cb78f55912874ddcf 100644 (file)
--- a/test/CodeGen/Thumb2/mve-fp-negabs.ll
+++ b/test/CodeGen/Thumb2/mve-fp-negabs.ll
@@ -8,17 +8,15 @@ define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
 ; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
 ; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    movs r2, #0
 ; CHECK-MVE-NEXT:    vneg.f16 s4, s4
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov s4, r1
 ; CHECK-MVE-NEXT:    vneg.f16 s4, s4
 ; CHECK-MVE-NEXT:    vmov r1, s4
-; CHECK-MVE-NEXT:    vdup.16 q1, r2
 ; CHECK-MVE-NEXT:    vmov.16 q1[0], r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
+; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vneg.f16 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
@@ -62,16 +60,11 @@ entry:
 define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
 ; CHECK-MVE-LABEL: fneg_float32_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vneg.f32 s7, s3
+; CHECK-MVE-NEXT:    vneg.f32 s6, s2
+; CHECK-MVE-NEXT:    vneg.f32 s5, s1
 ; CHECK-MVE-NEXT:    vneg.f32 s4, s0
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vneg.f32 s6, s1
-; CHECK-MVE-NEXT:    vneg.f32 s8, s2
-; CHECK-MVE-NEXT:    vneg.f32 s10, s3
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s4
-; CHECK-MVE-NEXT:    vmov.f32 s1, s6
-; CHECK-MVE-NEXT:    vmov.f32 s2, s8
-; CHECK-MVE-NEXT:    vmov.f32 s3, s10
+; CHECK-MVE-NEXT:    vmov q0, q1
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: fneg_float32_t:
@@ -89,17 +82,15 @@ define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
 ; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
 ; CHECK-MVE-NEXT:    vmov s4, r0
-; CHECK-MVE-NEXT:    movs r2, #0
 ; CHECK-MVE-NEXT:    vabs.f16 s4, s4
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov s4, r1
 ; CHECK-MVE-NEXT:    vabs.f16 s4, s4
 ; CHECK-MVE-NEXT:    vmov r1, s4
-; CHECK-MVE-NEXT:    vdup.16 q1, r2
 ; CHECK-MVE-NEXT:    vmov.16 q1[0], r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
+; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vabs.f16 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
@@ -143,16 +134,11 @@ entry:
 define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
 ; CHECK-MVE-LABEL: fabs_float32_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vabs.f32 s7, s3
+; CHECK-MVE-NEXT:    vabs.f32 s6, s2
+; CHECK-MVE-NEXT:    vabs.f32 s5, s1
 ; CHECK-MVE-NEXT:    vabs.f32 s4, s0
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vabs.f32 s6, s1
-; CHECK-MVE-NEXT:    vabs.f32 s8, s2
-; CHECK-MVE-NEXT:    vabs.f32 s10, s3
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s4
-; CHECK-MVE-NEXT:    vmov.f32 s1, s6
-; CHECK-MVE-NEXT:    vmov.f32 s2, s8
-; CHECK-MVE-NEXT:    vmov.f32 s3, s10
+; CHECK-MVE-NEXT:    vmov q0, q1
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: fabs_float32_t:

diff --git a/test/CodeGen/Thumb2/mve-shuffle.ll b/test/CodeGen/Thumb2/mve-shuffle.ll
index 59c99377146f9f6e8b91ad957fb042d4691ad445..87d209b5d2fd9d7dc2e725a65828a2cb23b453b7 100644 (file)
--- a/test/CodeGen/Thumb2/mve-shuffle.ll
+++ b/test/CodeGen/Thumb2/mve-shuffle.ll
@@ -310,49 +310,26 @@ entry:
 }
 
 define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {
-; CHECK-MVE-LABEL: shuffle1_f16:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    movs r2, #0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVE-NEXT:    vdup.16 q1, r2
-; CHECK-MVE-NEXT:    vmov.u16 r1, q0[6]
-; CHECK-MVE-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVE-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVE-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVE-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q1
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-MVEFP-LABEL: shuffle1_f16:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVEFP-NEXT:    vmov.u16 r1, q0[6]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVEFP-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q1
-; CHECK-MVEFP-NEXT:    bx lr
+; CHECK-LABEL: shuffle1_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u16 r0, q0[7]
+; CHECK-NEXT:    vmov.u16 r1, q0[6]
+; CHECK-NEXT:    vmov.16 q1[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[5]
+; CHECK-NEXT:    vmov.16 q1[1], r1
+; CHECK-NEXT:    vmov.16 q1[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[4]
+; CHECK-NEXT:    vmov.16 q1[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[3]
+; CHECK-NEXT:    vmov.16 q1[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-NEXT:    vmov.16 q1[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov.16 q1[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[0]
+; CHECK-NEXT:    vmov.16 q1[7], r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
 entry:
   %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <8 x half> %out
@@ -368,49 +345,26 @@ entry:
 }
 
 define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {
-; CHECK-MVE-LABEL: shuffle3_f16:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    movs r2, #0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVE-NEXT:    vdup.16 q1, r2
-; CHECK-MVE-NEXT:    vmov.u16 r1, q0[5]
-; CHECK-MVE-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVE-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVE-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVE-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVE-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
-; CHECK-MVE-NEXT:    vmov q0, q1
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-MVEFP-LABEL: shuffle3_f16:
-; CHECK-MVEFP:       @ %bb.0: @ %entry
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVEFP-NEXT:    vmov.u16 r1, q0[5]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVEFP-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[2]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVEFP-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVEFP-NEXT:    vmov.16 q1[7], r0
-; CHECK-MVEFP-NEXT:    vmov q0, q1
-; CHECK-MVEFP-NEXT:    bx lr
+; CHECK-LABEL: shuffle3_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u16 r0, q0[4]
+; CHECK-NEXT:    vmov.u16 r1, q0[5]
+; CHECK-NEXT:    vmov.16 q1[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[7]
+; CHECK-NEXT:    vmov.16 q1[1], r1
+; CHECK-NEXT:    vmov.16 q1[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[6]
+; CHECK-NEXT:    vmov.16 q1[3], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[3]
+; CHECK-NEXT:    vmov.16 q1[4], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[1]
+; CHECK-NEXT:    vmov.16 q1[5], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-NEXT:    vmov.16 q1[6], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[0]
+; CHECK-NEXT:    vmov.16 q1[7], r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
 entry:
   %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
   ret <8 x half> %out

diff --git a/test/CodeGen/Thumb2/mve-simple-arith.ll b/test/CodeGen/Thumb2/mve-simple-arith.ll
index 6d2478f8de14cb78e81f4f4dda74b5ef0634a334..570aae3f21be4f1b1cf2b08119587277e0a5f4da 100644 (file)
--- a/test/CodeGen/Thumb2/mve-simple-arith.ll
+++ b/test/CodeGen/Thumb2/mve-simple-arith.ll
@@ -35,16 +35,11 @@ entry:
 define arm_aapcs_vfpcc <4 x float> @add_float32_t(<4 x float> %src1, <4 x float> %src2) {
 ; CHECK-MVE-LABEL: add_float32_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vadd.f32 s11, s7, s3
+; CHECK-MVE-NEXT:    vadd.f32 s10, s6, s2
+; CHECK-MVE-NEXT:    vadd.f32 s9, s5, s1
 ; CHECK-MVE-NEXT:    vadd.f32 s8, s4, s0
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vadd.f32 s10, s5, s1
-; CHECK-MVE-NEXT:    vadd.f32 s12, s6, s2
-; CHECK-MVE-NEXT:    vadd.f32 s4, s7, s3
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s8
-; CHECK-MVE-NEXT:    vmov.f32 s1, s10
-; CHECK-MVE-NEXT:    vmov.f32 s2, s12
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
+; CHECK-MVE-NEXT:    vmov q0, q2
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: add_float32_t:
@@ -60,25 +55,23 @@ define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %s
 ; CHECK-MVE-LABEL: add_float16_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[0]
-; CHECK-MVE-NEXT:    vmov s10, r1
 ; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
 ; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    movs r2, #0
+; CHECK-MVE-NEXT:    vmov.u16 r0, q1[0]
+; CHECK-MVE-NEXT:    vmov s10, r0
+; CHECK-MVE-NEXT:    vmov.u16 r2, q1[1]
 ; CHECK-MVE-NEXT:    vadd.f16 s8, s10, s8
+; CHECK-MVE-NEXT:    vmov s10, r2
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov s8, r1
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[1]
-; CHECK-MVE-NEXT:    vmov s10, r1
 ; CHECK-MVE-NEXT:    vadd.f16 s8, s10, s8
 ; CHECK-MVE-NEXT:    vmov r1, s8
-; CHECK-MVE-NEXT:    vdup.16 q2, r2
 ; CHECK-MVE-NEXT:    vmov.16 q2[0], r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
 ; CHECK-MVE-NEXT:    vmov s12, r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q1[2]
 ; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
 ; CHECK-MVE-NEXT:    vadd.f16 s12, s14, s12
 ; CHECK-MVE-NEXT:    vmov r0, s12
 ; CHECK-MVE-NEXT:    vmov.16 q2[2], r0
@@ -163,16 +156,11 @@ entry:
 define arm_aapcs_vfpcc <4 x float> @sub_float32_t(<4 x float> %src1, <4 x float> %src2) {
 ; CHECK-MVE-LABEL: sub_float32_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vsub.f32 s11, s7, s3
+; CHECK-MVE-NEXT:    vsub.f32 s10, s6, s2
+; CHECK-MVE-NEXT:    vsub.f32 s9, s5, s1
 ; CHECK-MVE-NEXT:    vsub.f32 s8, s4, s0
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vsub.f32 s10, s5, s1
-; CHECK-MVE-NEXT:    vsub.f32 s12, s6, s2
-; CHECK-MVE-NEXT:    vsub.f32 s4, s7, s3
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s8
-; CHECK-MVE-NEXT:    vmov.f32 s1, s10
-; CHECK-MVE-NEXT:    vmov.f32 s2, s12
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
+; CHECK-MVE-NEXT:    vmov q0, q2
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: sub_float32_t:
@@ -188,25 +176,23 @@ define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %s
 ; CHECK-MVE-LABEL: sub_float16_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[0]
-; CHECK-MVE-NEXT:    vmov s10, r1
 ; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
 ; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    movs r2, #0
+; CHECK-MVE-NEXT:    vmov.u16 r0, q1[0]
+; CHECK-MVE-NEXT:    vmov s10, r0
+; CHECK-MVE-NEXT:    vmov.u16 r2, q1[1]
 ; CHECK-MVE-NEXT:    vsub.f16 s8, s10, s8
+; CHECK-MVE-NEXT:    vmov s10, r2
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov s8, r1
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[1]
-; CHECK-MVE-NEXT:    vmov s10, r1
 ; CHECK-MVE-NEXT:    vsub.f16 s8, s10, s8
 ; CHECK-MVE-NEXT:    vmov r1, s8
-; CHECK-MVE-NEXT:    vdup.16 q2, r2
 ; CHECK-MVE-NEXT:    vmov.16 q2[0], r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
 ; CHECK-MVE-NEXT:    vmov s12, r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q1[2]
 ; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
 ; CHECK-MVE-NEXT:    vsub.f16 s12, s14, s12
 ; CHECK-MVE-NEXT:    vmov r0, s12
 ; CHECK-MVE-NEXT:    vmov.16 q2[2], r0
@@ -291,25 +277,23 @@ define arm_aapcs_vfpcc <8 x half> @mul_float16_t(<8 x half> %src1, <8 x half> %s
 ; CHECK-MVE-LABEL: mul_float16_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[0]
-; CHECK-MVE-NEXT:    vmov s10, r1
 ; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
 ; CHECK-MVE-NEXT:    vmov s8, r0
-; CHECK-MVE-NEXT:    movs r2, #0
+; CHECK-MVE-NEXT:    vmov.u16 r0, q1[0]
+; CHECK-MVE-NEXT:    vmov s10, r0
+; CHECK-MVE-NEXT:    vmov.u16 r2, q1[1]
 ; CHECK-MVE-NEXT:    vmul.f16 s8, s10, s8
+; CHECK-MVE-NEXT:    vmov s10, r2
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov s8, r1
-; CHECK-MVE-NEXT:    vmov.u16 r1, q1[1]
-; CHECK-MVE-NEXT:    vmov s10, r1
 ; CHECK-MVE-NEXT:    vmul.f16 s8, s10, s8
 ; CHECK-MVE-NEXT:    vmov r1, s8
-; CHECK-MVE-NEXT:    vdup.16 q2, r2
 ; CHECK-MVE-NEXT:    vmov.16 q2[0], r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
 ; CHECK-MVE-NEXT:    vmov s12, r0
 ; CHECK-MVE-NEXT:    vmov.u16 r0, q1[2]
 ; CHECK-MVE-NEXT:    vmov s14, r0
-; CHECK-MVE-NEXT:    vmov.16 q2[1], r1
 ; CHECK-MVE-NEXT:    vmul.f16 s12, s14, s12
 ; CHECK-MVE-NEXT:    vmov r0, s12
 ; CHECK-MVE-NEXT:    vmov.16 q2[2], r0
@@ -363,16 +347,11 @@ entry:
 define arm_aapcs_vfpcc <4 x float> @mul_float32_t(<4 x float> %src1, <4 x float> %src2) {
 ; CHECK-MVE-LABEL: mul_float32_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vmul.f32 s11, s7, s3
+; CHECK-MVE-NEXT:    vmul.f32 s10, s6, s2
+; CHECK-MVE-NEXT:    vmul.f32 s9, s5, s1
 ; CHECK-MVE-NEXT:    vmul.f32 s8, s4, s0
-; CHECK-MVE-NEXT:    movs r0, #0
-; CHECK-MVE-NEXT:    vmul.f32 s10, s5, s1
-; CHECK-MVE-NEXT:    vmul.f32 s12, s6, s2
-; CHECK-MVE-NEXT:    vmul.f32 s4, s7, s3
-; CHECK-MVE-NEXT:    vdup.32 q0, r0
-; CHECK-MVE-NEXT:    vmov.f32 s0, s8
-; CHECK-MVE-NEXT:    vmov.f32 s1, s10
-; CHECK-MVE-NEXT:    vmov.f32 s2, s12
-; CHECK-MVE-NEXT:    vmov.f32 s3, s4
+; CHECK-MVE-NEXT:    vmov q0, q2
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: mul_float32_t:

diff --git a/test/CodeGen/Thumb2/mve-soft-float-abi.ll b/test/CodeGen/Thumb2/mve-soft-float-abi.ll
new file mode 100644 (file)
index 0000000..794f7ba
--- /dev/null
+++ b/test/CodeGen/Thumb2/mve-soft-float-abi.ll
@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FP %s
+
+define <16 x i8> @vector_add_i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK-LABEL: vector_add_i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov d1, r2, r3
+; CHECK-NEXT:    vmov d0, r0, r1
+; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vadd.i8 q0, q0, q1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %sum = add <16 x i8> %lhs, %rhs
+  ret <16 x i8> %sum
+}
+
+define <8 x i16> @vector_add_i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK-LABEL: vector_add_i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov d1, r2, r3
+; CHECK-NEXT:    vmov d0, r0, r1
+; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vadd.i16 q0, q0, q1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %sum = add <8 x i16> %lhs, %rhs
+  ret <8 x i16> %sum
+}
+
+define <4 x i32> @vector_add_i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: vector_add_i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov d1, r2, r3
+; CHECK-NEXT:    vmov d0, r0, r1
+; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vadd.i32 q0, q0, q1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %sum = add <4 x i32> %lhs, %rhs
+  ret <4 x i32> %sum
+}
+
+define <8 x half> @vector_add_f16(<8 x half> %lhs, <8 x half> %rhs) {
+; CHECK-FP-LABEL: vector_add_f16:
+; CHECK-FP:       @ %bb.0: @ %entry
+; CHECK-FP-NEXT:    vmov d1, r2, r3
+; CHECK-FP-NEXT:    vmov d0, r0, r1
+; CHECK-FP-NEXT:    mov r0, sp
+; CHECK-FP-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-FP-NEXT:    vadd.f16 q0, q0, q1
+; CHECK-FP-NEXT:    vmov r0, r1, d0
+; CHECK-FP-NEXT:    vmov r2, r3, d1
+; CHECK-FP-NEXT:    bx lr
+entry:
+  %sum = fadd <8 x half> %lhs, %rhs
+  ret <8 x half> %sum
+}
+
+define <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK-FP-LABEL: vector_add_f32:
+; CHECK-FP:       @ %bb.0: @ %entry
+; CHECK-FP-NEXT:    vmov d1, r2, r3
+; CHECK-FP-NEXT:    vmov d0, r0, r1
+; CHECK-FP-NEXT:    mov r0, sp
+; CHECK-FP-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-FP-NEXT:    vadd.f32 q0, q0, q1
+; CHECK-FP-NEXT:    vmov r0, r1, d0
+; CHECK-FP-NEXT:    vmov r2, r3, d1
+; CHECK-FP-NEXT:    bx lr
+entry:
+  %sum = fadd <4 x float> %lhs, %rhs
+  ret <4 x float> %sum
+}