R600/SI: Remove some unnecessary patterns from VINTRP multiclass

DisableEncoding and Constraints can be set using let statements around
the multiclass defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238148 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 12e9d4f24bb0820d7ea49adc2c0e9baac2eba669..587ddb5cd1a821a2021ea0b92e49a0060f14b94c 100644 (file)
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -1771,16 +1771,12 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
   SIMCInstr<opName, SISubtarget.VI>;
 
 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
-                     list<dag> pattern = [],
-                     string disableEncoding = "", string constraints = ""> {
-  let DisableEncoding = disableEncoding,
-      Constraints = constraints in {
-    def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
+                     list<dag> pattern = []> {
+  def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
 
-    def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
+  def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
 
-    def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
-  }
+  def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 15c2f3ec193a64163a1e9217584072dffe97a67e..d92c4b62398b164554977cdf9d8aac75f1da3232 100644 (file)
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1461,15 +1461,17 @@ defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
 
 } // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"
 
+let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
+
 defm V_INTERP_P2_F32 : VINTRP_m <
   0x00000001,
   (outs VGPR_32:$dst),
   (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
   "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
   [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
-                                                     (i32 imm:$attr)))],
-  "$src0",
-  "$src0 = $dst">;
+                                                     (i32 imm:$attr)))]>;
+
+} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
 
 defm V_INTERP_MOV_F32 : VINTRP_m <
   0x00000002,