[InstCombine][XOP] The instructions for the scalar frcz intrinsics are defined to...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289411 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 839eff7cb75b753dea9ddff5090209f85b2dd6eb..abda6a366e80d1ffe42c6f770814cb08d1a214e0 100644 (file)
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1255,13 +1255,25 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
     switch (II->getIntrinsicID()) {
     default: break;
 
+    case Intrinsic::x86_xop_vfrcz_ss:
+    case Intrinsic::x86_xop_vfrcz_sd:
+      // The instructions for these intrinsics are speced to zero upper bits not
+      // pass them through like other scalar intrinsics. So we shouldn't just
+      // use Arg0 if DemandedElts[0] is clear like we do for other intrinsics.
+      // Instead we should return a zero vector.
+      if (!DemandedElts[0])
+        return ConstantAggregateZero::get(II->getType());
+
+      TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
+                                        UndefElts, Depth + 1);
+      if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
+      break;
+
     // Unary scalar-as-vector operations that work column-wise.
     case Intrinsic::x86_sse_rcp_ss:
     case Intrinsic::x86_sse_rsqrt_ss:
     case Intrinsic::x86_sse_sqrt_ss:
     case Intrinsic::x86_sse2_sqrt_sd:
-    case Intrinsic::x86_xop_vfrcz_ss:
-    case Intrinsic::x86_xop_vfrcz_sd:
       TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
                                         UndefElts, Depth + 1);
       if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }

diff --git a/test/Transforms/InstCombine/x86-xop.ll b/test/Transforms/InstCombine/x86-xop.ll
index 015d511ac4d44ee783c5d129bf7f7b8f73f0f622..d987c757da50540148f470373f40f567b19a4fe9 100644 (file)
--- a/test/Transforms/InstCombine/x86-xop.ll
+++ b/test/Transforms/InstCombine/x86-xop.ll
@@ -17,7 +17,7 @@ define double @test_vfrcz_sd_0(double %a) {
 
 define double @test_vfrcz_sd_1(double %a) {
 ; CHECK-LABEL: @test_vfrcz_sd_1(
-; CHECK-NEXT:    ret double 1.000000e+00
+; CHECK-NEXT:    ret double 0.000000e+00
 ;
   %1 = insertelement <2 x double> undef, double %a, i32 0
   %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
@@ -44,7 +44,7 @@ define float @test_vfrcz_ss_0(float %a) {
 
 define float @test_vfrcz_ss_3(float %a) {
 ; CHECK-LABEL: @test_vfrcz_ss_3(
-; CHECK-NEXT:    ret float 3.000000e+00
+; CHECK-NEXT:    ret float 0.000000e+00
 ;
   %1 = insertelement <4 x float> undef, float %a, i32 0
   %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1