[InstSimplify] Add test case to show bad sign bit handling for integer abs idiom...

computeKnownBits will indicate the sign bit of abs is 0 if the
the RHS operand returned by matchSelectPattern has the nsw flag set.
For abs idioms like (X >= 0) ? X : -X, the RHS returns -X. But
we can also match ((X-Y) >= 0 ? X-Y : Y-X as abs. In this case
RHS will be the Y-X operand. According to Alive, the sign bit for
this is only 0 if both the X-Y and Y-X operands have the nsw flag.
But we're only checking the Y-X operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367747 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstSimplify/icmp-abs-nabs.ll b/test/Transforms/InstSimplify/icmp-abs-nabs.ll
index be2e7b4d4a609860dada3f9fa8ff5d579bd47a07..5f38194fe33c96cc7ecc182e937fadbf72a01b13 100644 (file)
--- a/test/Transforms/InstSimplify/icmp-abs-nabs.ll
+++ b/test/Transforms/InstSimplify/icmp-abs-nabs.ll
@@ -401,3 +401,15 @@ define i1 @nabs_no_intersection(i32 %a) {
   ret i1 %r
 }
 
+; We can't fold this to false unless both subs have nsw.
+define i1 @abs_sub_sub_missing_nsw(i32 %x, i32 %y) {
+; CHECK-LABEL: @abs_sub_sub_missing_nsw(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = sub i32 %x, %y
+  %b = sub nsw i32 %y, %x
+  %c = icmp sgt i32 %a, -1
+  %d = select i1 %c, i32 %a, i32 %b
+  %e = icmp slt i32 %d, 0
+  ret i1 %e
+}