[AArch64] Add V8_2aOps feature to Cortex-A55 and 75

Add the missing hardware features the ProcA55 and ProcA75 feature.
These are already enabled via the target parser, but I had missed
them in the backend.

Differential Revision: https://reviews.llvm.org/D37974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313535 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td
index 8ff7f40ade4d67a9f18a425b6720610038b12fb7..8d2934ee8abefe9f29cdc1697e2c8a7b147b99d0 100644 (file)
--- a/lib/Target/AArch64/AArch64.td
+++ b/lib/Target/AArch64/AArch64.td
@@ -215,6 +215,7 @@ def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 
 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
                                    "Cortex-A55 ARM processors", [
+                                   HasV8_2aOps,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureFuseAES,
@@ -262,6 +263,7 @@ def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 
 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
                                    "Cortex-A75 ARM processors", [
+                                   HasV8_2aOps,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureFuseAES,

diff --git a/test/MC/AArch64/armv8.1a-lse.s b/test/MC/AArch64/armv8.1a-lse.s
index 6143d0e138003a36a07b6f881582e4ded9a9ad40..3da5e3c97b74405b99939d93ecc7f280f2678099 100644 (file)
--- a/test/MC/AArch64/armv8.1a-lse.s
+++ b/test/MC/AArch64/armv8.1a-lse.s
@@ -1,4 +1,8 @@
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a,+lse -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
   .text
 

diff --git a/test/MC/AArch64/crc.s b/test/MC/AArch64/crc.s
index f0e4a5aa7531b836505b6ac9ccf4da42a7561229..597ba3c257a9f1d2e6704c2a6bfc4a282dc6a55f 100644 (file)
--- a/test/MC/AArch64/crc.s
+++ b/test/MC/AArch64/crc.s
@@ -1,6 +1,11 @@
 // RUN: llvm-mc -triple aarch64-- -mattr=+crc %s 2>&1 |\
 // RUN:   FileCheck %s --check-prefix=CRC
 
+// RUN: llvm-mc -triple aarch64-- -mcpu=cortex-a55 %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=CRC
+// RUN: llvm-mc -triple aarch64-- -mcpu=cortex-a75 %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=CRC
+
 // RUN: not llvm-mc -triple aarch64-- %s 2>&1 |\
 // RUN:   FileCheck %s --check-prefix=NOCRC
 // RUN: not llvm-mc -triple aarch64-- -mcpu=cyclone %s 2>&1 |\

diff --git a/test/MC/AArch64/ras-extension.s b/test/MC/AArch64/ras-extension.s
index ac4a8099e35908c6cd6d1b7221915fac06bb594e..e8d1f62e6bd1e86e9072dd012277c05c63dbfe2a 100644 (file)
--- a/test/MC/AArch64/ras-extension.s
+++ b/test/MC/AArch64/ras-extension.s
@@ -1,4 +1,6 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ras < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s | FileCheck %s
 
   esb
 // CHECK: esb                             // encoding: [0x1f,0x22,0x03,0xd5]