[InstCombine] add funnel shift tests with arbitrary constants; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356367 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstCombine/fsh.ll b/test/Transforms/InstCombine/fsh.ll
index 63163ac7e1864b3ff2123b8a7248ff16fb80bb61..2a91a60e2c8e7276cfca04016e101401a2566c25 100644 (file)
--- a/test/Transforms/InstCombine/fsh.ll
+++ b/test/Transforms/InstCombine/fsh.ll
@@ -215,8 +215,8 @@ define i33 @fshr_op1_zero(i33 %x) {
   ret i33 %r
 }
 
-define <2 x i31> @fshl_op0_zero_vec(<2 x i31> %x) {
-; CHECK-LABEL: @fshl_op0_zero_vec(
+define <2 x i31> @fshl_op0_zero_splat_vec(<2 x i31> %x) {
+; CHECK-LABEL: @fshl_op0_zero_splat_vec(
 ; CHECK-NEXT:    [[R:%.*]] = lshr <2 x i31> [[X:%.*]], <i31 24, i31 24>
 ; CHECK-NEXT:    ret <2 x i31> [[R]]
 ;
@@ -224,8 +224,8 @@ define <2 x i31> @fshl_op0_zero_vec(<2 x i31> %x) {
   ret <2 x i31> %r
 }
 
-define <2 x i31> @fshl_op1_undef_vec(<2 x i31> %x) {
-; CHECK-LABEL: @fshl_op1_undef_vec(
+define <2 x i31> @fshl_op1_undef_splat_vec(<2 x i31> %x) {
+; CHECK-LABEL: @fshl_op1_undef_splat_vec(
 ; CHECK-NEXT:    [[R:%.*]] = shl <2 x i31> [[X:%.*]], <i31 7, i31 7>
 ; CHECK-NEXT:    ret <2 x i31> [[R]]
 ;
@@ -233,8 +233,8 @@ define <2 x i31> @fshl_op1_undef_vec(<2 x i31> %x) {
   ret <2 x i31> %r
 }
 
-define <2 x i32> @fshr_op0_undef_vec(<2 x i32> %x) {
-; CHECK-LABEL: @fshr_op0_undef_vec(
+define <2 x i32> @fshr_op0_undef_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @fshr_op0_undef_splat_vec(
 ; CHECK-NEXT:    [[R:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 7, i32 7>
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -242,8 +242,8 @@ define <2 x i32> @fshr_op0_undef_vec(<2 x i32> %x) {
   ret <2 x i32> %r
 }
 
-define <2 x i32> @fshr_op1_zero_vec(<2 x i32> %x) {
-; CHECK-LABEL: @fshr_op1_zero_vec(
+define <2 x i32> @fshr_op1_zero_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @fshr_op1_zero_splat_vec(
 ; CHECK-NEXT:    [[R:%.*]] = shl <2 x i32> [[X:%.*]], <i32 25, i32 25>
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -251,6 +251,42 @@ define <2 x i32> @fshr_op1_zero_vec(<2 x i32> %x) {
   ret <2 x i32> %r
 }
 
+define <2 x i31> @fshl_op0_zero_vec(<2 x i31> %x) {
+; CHECK-LABEL: @fshl_op0_zero_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> zeroinitializer, <2 x i31> [[X:%.*]], <2 x i31> <i31 1, i31 2>)
+; CHECK-NEXT:    ret <2 x i31> [[R]]
+;
+  %r = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> zeroinitializer, <2 x i31> %x, <2 x i31> <i31 -1, i31 33>)
+  ret <2 x i31> %r
+}
+
+define <2 x i31> @fshl_op1_undef_vec(<2 x i31> %x) {
+; CHECK-LABEL: @fshl_op1_undef_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[X:%.*]], <2 x i31> undef, <2 x i31> <i31 1, i31 2>)
+; CHECK-NEXT:    ret <2 x i31> [[R]]
+;
+  %r = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> %x, <2 x i31> undef, <2 x i31> <i31 -1, i31 33>)
+  ret <2 x i31> %r
+}
+
+define <2 x i32> @fshr_op0_undef_vec(<2 x i32> %x) {
+; CHECK-LABEL: @fshr_op0_undef_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> undef, <2 x i32> [[X:%.*]], <2 x i32> <i32 31, i32 1>)
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %r = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> undef, <2 x i32> %x, <2 x i32> <i32 -1, i32 33>)
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @fshr_op1_zero_vec(<2 x i32> %x) {
+; CHECK-LABEL: @fshr_op1_zero_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> [[X:%.*]], <2 x i32> zeroinitializer, <2 x i32> <i32 31, i32 1>)
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %r = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> zeroinitializer, <2 x i32> <i32 -1, i32 33>)
+  ret <2 x i32> %r
+}
+
 ; Only demand bits from one of the operands.
 
 define i32 @fshl_only_op0_demanded(i32 %x, i32 %y) {