[DAGCombine] Make sure we check the ResNo from UADDO before combining

Summary: UADDO has 2 result, and one must check the result no before doing any kind of combine. Without it, the transform is invalid.

Reviewers: joerg

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305162 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a0967f574006bfc1c714ceed2b8f3854d2d235e5..68f3bf354934c5fc2ac17545b0b9047269dcfa20 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2217,7 +2217,8 @@ SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
                                        SDNode *N) {
   // Iff the flag result is dead:
   // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
-  if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::UADDO) &&
+  if ((N0.getOpcode() == ISD::ADD ||
+       (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0)) &&
       isNullConstant(N1) && !N->hasAnyUseOfValue(1))
     return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
                        N0.getOperand(0), N0.getOperand(1), CarryIn);

diff --git a/test/CodeGen/X86/addcarry.ll b/test/CodeGen/X86/addcarry.ll
index 3c84af4aa9ec6457e1d38eb036ca235b26a62c75..cffcfd8e8a42663319ff611bbd28cb6d47fb384d 100644 (file)
--- a/test/CodeGen/X86/addcarry.ll
+++ b/test/CodeGen/X86/addcarry.ll
@@ -81,6 +81,30 @@ entry:
  ret void
 }
 
+define i8 @e(i32* nocapture %a, i32 %b) nounwind {
+; CHECK-LABEL: e:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    # kill: %ESI<def> %ESI<kill> %RSI<def>
+; CHECK-NEXT:    movl (%rdi), %ecx
+; CHECK-NEXT:    leal (%rsi,%rcx), %edx
+; CHECK-NEXT:    addl %esi, %edx
+; CHECK-NEXT:    setb %al
+; CHECK-NEXT:    addl %esi, %ecx
+; CHECK-NEXT:    movl %edx, (%rdi)
+; CHECK-NEXT:    adcb $0, %al
+; CHECK-NEXT:    retq
+  %1 = load i32, i32* %a, align 4
+  %2 = add i32 %1, %b
+  %3 = icmp ult i32 %2, %b
+  %4 = zext i1 %3 to i8
+  %5 = add i32 %2, %b
+  store i32 %5, i32* %a, align 4
+  %6 = icmp ult i32 %5, %b
+  %7 = zext i1 %6 to i8
+  %8 = add nuw nsw i8 %7, %4
+  ret i8 %8
+}
+
 %scalar = type { [4 x i64] }
 
 define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) {