AMDGPU: Fix trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294694 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
index edeb485518dbe1fbc41e1eda5b2fc55462a87561..5935c6a49f09694e5a0e8586b2ac69e18b72be35 100644 (file)
--- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -160,7 +160,7 @@ AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
                                                        StringRef ArchName) {
   uint16_t VendorNameSize = VendorName.size() + 1;
   uint16_t ArchNameSize = ArchName.size() + 1;
-  
+
   unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
     sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
     VendorNameSize + ArchNameSize;

diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
index ba3a623221216c366e0e34922e95d80d0f79274c..5c8aee79fdb1a0f15bb7febd3c75aa96df253f0c 100644 (file)
--- a/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1782,7 +1782,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
   switch (MI.getOpcode()) {
   case AMDGPU::S_TRAP_PSEUDO: {
     const DebugLoc &DL = MI.getDebugLoc();
-    const int TrapType = MI.getOperand(0).getImm(); 
+    const int TrapType = MI.getOperand(0).getImm();
 
     if (Subtarget->getTrapHandlerAbi() == SISubtarget::TrapHandlerAbiHsa &&
         Subtarget->isTrapHandlerEnabled()) {
@@ -1798,11 +1798,11 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
       BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::SGPR0_SGPR1)
         .addReg(UserSGPR);
       BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_TRAP))
-             .addImm(TrapType)
+        .addImm(TrapType)
         .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit);
     } else {
-      switch (TrapType) {      
-      case SISubtarget::TrapCodeLLVMTrap: 
+      switch (TrapType) {
+      case SISubtarget::TrapCodeLLVMTrap:
         BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM));
         break;
       case SISubtarget::TrapCodeLLVMDebugTrap: {
@@ -1810,7 +1810,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
                                          "debugtrap handler not supported",
                                          DL,
                                          DS_Warning);
-        LLVMContext &C = MF->getFunction()->getContext();         
+        LLVMContext &C = MF->getFunction()->getContext();
         C.diagnose(NoTrap);
         BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_NOP))
           .addImm(0);
@@ -1824,7 +1824,6 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
     MI.eraseFromParent();
     return BB;
   }
-
   case AMDGPU::SI_INIT_M0:
     BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
             TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)

diff --git a/lib/Target/AMDGPU/VOP1Instructions.td b/lib/Target/AMDGPU/VOP1Instructions.td
index 15abed4a76b56d271e515475f3a59859ca72216e..c023dfec7923d2f6ac182c85807f4b38e6196ac0 100644 (file)
--- a/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/lib/Target/AMDGPU/VOP1Instructions.td
@@ -23,7 +23,7 @@ class VOP1e <bits<8> op, VOPProfile P> : Enc32 {
 
 class VOP1_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
   bits<8> vdst;
-  
+
   let Inst{8-0}   = 0xf9; // sdwa
   let Inst{16-9}  = op;
   let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);

diff --git a/lib/Target/AMDGPU/VOP2Instructions.td b/lib/Target/AMDGPU/VOP2Instructions.td
index cd5f044ecd5388f74f0dc7eb38d3e64206cb3980..01075c3a0b7db97256b57a612e2d0363a85b1b61 100644 (file)
--- a/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/lib/Target/AMDGPU/VOP2Instructions.td
@@ -40,7 +40,7 @@ class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
 class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
   bits<8> vdst;
   bits<8> src1;
-  
+
   let Inst{8-0}   = 0xf9; // sdwa
   let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
   let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
@@ -133,7 +133,7 @@ multiclass VOP2bInst <string opName,
     let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
       def _e32 : VOP2_Pseudo <opName, P>,
                  Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
-      
+
       def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
     }
 
@@ -654,7 +654,7 @@ multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
   VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
 
 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
- 
+
 multiclass VOP2_SDWA_Real <bits<6> op> {
   def _sdwa_vi :
     VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,

diff --git a/lib/Target/AMDGPU/VOPInstructions.td b/lib/Target/AMDGPU/VOPInstructions.td
index 184c5bc9bb59568439fefd293b32fb1b728ea29c..ebc01ffc3af738a15a2e59e2177f7e20638ad5db 100644 (file)
--- a/lib/Target/AMDGPU/VOPInstructions.td
+++ b/lib/Target/AMDGPU/VOPInstructions.td
@@ -250,7 +250,7 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
   VOP <opName>,
   SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE>,
   MnemonicAlias <opName#"_sdwa", opName> {
-  
+
   let isPseudo = 1;
   let isCodeGenOnly = 1;
   let UseNamedOperandTable = 1;
@@ -261,12 +261,12 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
   let Size = 8;
   let mayLoad = 0;
   let mayStore = 0;
-  let hasSideEffects = 0;  
+  let hasSideEffects = 0;
 
   let VALU = 1;
   let SDWA = 1;
   let Uses = [EXEC];
-  
+
   let SubtargetPredicate = HasSDWA;
   let AssemblerPredicate = !if(P.HasExt, HasSDWA, DisableInst);
   let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.SDWA,