linux/aarch64/ioctls_inc0.h \
linux/aarch64/ioctls_inc1.h \
linux/aarch64/nr_prefix.c \
+ linux/aarch64/raw_syscall.h \
linux/aarch64/set_error.c \
linux/aarch64/set_scno.c \
linux/aarch64/shuffle_scno.c \
linux/alpha/get_syscall_result.c \
linux/alpha/ioctls_arch0.h \
linux/alpha/ioctls_inc0.h \
+ linux/alpha/raw_syscall.h \
linux/alpha/set_error.c \
linux/alpha/set_scno.c \
linux/alpha/signalent.h \
linux/arc/get_syscall_args.c \
linux/arc/ioctls_arch0.h \
linux/arc/ioctls_inc0.h \
+ linux/arc/raw_syscall.h \
linux/arc/set_error.c \
linux/arc/set_scno.c \
linux/arc/syscallent.h \
linux/arm/ioctls_arch0.h \
linux/arm/ioctls_inc0.h \
linux/arm/nr_prefix.c \
+ linux/arm/raw_syscall.h \
linux/arm/set_error.c \
linux/arm/set_scno.c \
linux/arm/shuffle_scno.c \
linux/avr32/get_syscall_args.c \
linux/avr32/ioctls_arch0.h \
linux/avr32/ioctls_inc0.h \
+ linux/avr32/raw_syscall.h \
linux/avr32/set_error.c \
linux/avr32/set_scno.c \
linux/avr32/syscallent.h \
linux/bfin/get_syscall_result.c \
linux/bfin/ioctls_arch0.h \
linux/bfin/ioctls_inc0.h \
+ linux/bfin/raw_syscall.h \
linux/bfin/rt_sigframe.h \
linux/bfin/set_error.c \
linux/bfin/set_scno.c \
linux/hppa/get_syscall_result.c \
linux/hppa/ioctls_arch0.h \
linux/hppa/ioctls_inc0.h \
+ linux/hppa/raw_syscall.h \
linux/hppa/rt_sigframe.h \
linux/hppa/set_error.c \
linux/hppa/set_scno.c \
linux/i386/get_syscall_args.c \
linux/i386/ioctls_arch0.h \
linux/i386/ioctls_inc0.h \
+ linux/i386/raw_syscall.h \
linux/i386/rt_sigframe.h \
linux/i386/set_error.c \
linux/i386/set_scno.c \
linux/ia64/get_syscall_args.c \
linux/ia64/ioctls_arch0.h \
linux/ia64/ioctls_inc0.h \
+ linux/ia64/raw_syscall.h \
linux/ia64/rt_sigframe.h \
linux/ia64/set_error.c \
linux/ia64/set_scno.c \
linux/m68k/get_syscall_args.c \
linux/m68k/ioctls_arch0.h \
linux/m68k/ioctls_inc0.h \
+ linux/m68k/raw_syscall.h \
linux/m68k/rt_sigframe.h \
linux/m68k/set_error.c \
linux/m68k/set_scno.c \
linux/metag/get_syscall_args.c \
linux/metag/ioctls_arch0.h \
linux/metag/ioctls_inc0.h \
+ linux/metag/raw_syscall.h \
linux/metag/set_error.c \
linux/metag/set_scno.c \
linux/metag/syscallent.h \
linux/microblaze/get_syscall_result.c \
linux/microblaze/ioctls_arch0.h \
linux/microblaze/ioctls_inc0.h \
+ linux/microblaze/raw_syscall.h \
linux/microblaze/set_error.c \
linux/microblaze/set_scno.c \
linux/microblaze/syscallent.h \
linux/mips/get_syscall_args.c \
linux/mips/ioctls_arch0.h \
linux/mips/ioctls_inc0.h \
+ linux/mips/raw_syscall.h \
linux/mips/rt_sigframe.h \
linux/mips/set_error.c \
linux/mips/set_scno.c \
linux/nios2/get_syscall_args.c \
linux/nios2/ioctls_arch0.h \
linux/nios2/ioctls_inc0.h \
+ linux/nios2/raw_syscall.h \
linux/nios2/set_error.c \
linux/nios2/set_scno.c \
linux/nios2/syscallent.h \
linux/or1k/get_syscall_args.c \
linux/or1k/ioctls_arch0.h \
linux/or1k/ioctls_inc0.h \
+ linux/or1k/raw_syscall.h \
linux/or1k/set_error.c \
linux/or1k/set_scno.c \
linux/or1k/syscallent.h \
linux/powerpc/getregs_old.h \
linux/powerpc/ioctls_arch0.h \
linux/powerpc/ioctls_inc0.h \
+ linux/powerpc/raw_syscall.h \
linux/powerpc/set_error.c \
linux/powerpc/set_scno.c \
linux/powerpc/syscallent.h \
linux/powerpc64/ioctls_arch1.h \
linux/powerpc64/ioctls_inc0.h \
linux/powerpc64/ioctls_inc1.h \
+ linux/powerpc64/raw_syscall.h \
linux/powerpc64/rt_sigframe.h \
linux/powerpc64/set_error.c \
linux/powerpc64/set_scno.c \
linux/powerpc64/syscallent.h \
linux/powerpc64/syscallent1.h \
linux/powerpc64/userent.h \
+ linux/raw_syscall.h \
linux/riscv/arch_defs_.h \
linux/riscv/arch_regs.c \
linux/riscv/arch_regs.h \
linux/riscv/ioctls_arch1.h \
linux/riscv/ioctls_inc0.h \
linux/riscv/ioctls_inc1.h \
+ linux/riscv/raw_syscall.h \
linux/riscv/set_error.c \
linux/riscv/set_scno.c \
linux/riscv/signalent1.h \
linux/s390/get_syscall_args.c \
linux/s390/ioctls_arch0.h \
linux/s390/ioctls_inc0.h \
+ linux/s390/raw_syscall.h \
linux/s390/rt_sigframe.h \
linux/s390/set_error.c \
linux/s390/set_scno.c \
linux/s390x/ioctls_arch1.h \
linux/s390x/ioctls_inc0.h \
linux/s390x/ioctls_inc1.h \
+ linux/s390x/raw_syscall.h \
linux/s390x/rt_sigframe.h \
linux/s390x/set_error.c \
linux/s390x/set_scno.c \
linux/sh/get_syscall_result.c \
linux/sh/ioctls_arch0.h \
linux/sh/ioctls_inc0.h \
+ linux/sh/raw_syscall.h \
linux/sh/set_error.c \
linux/sh/set_scno.c \
linux/sh/syscallent.h \
linux/sh64/get_syscall_result.c \
linux/sh64/ioctls_arch0.h \
linux/sh64/ioctls_inc0.h \
+ linux/sh64/raw_syscall.h \
linux/sh64/rt_sigframe.h \
linux/sh64/set_error.c \
linux/sh64/set_scno.c \
linux/sparc/get_syscall_args.c \
linux/sparc/ioctls_arch0.h \
linux/sparc/ioctls_inc0.h \
+ linux/sparc/raw_syscall.h \
linux/sparc/rt_sigframe.h \
linux/sparc/set_error.c \
linux/sparc/set_scno.c \
linux/sparc64/ioctls_arch1.h \
linux/sparc64/ioctls_inc0.h \
linux/sparc64/ioctls_inc1.h \
+ linux/sparc64/raw_syscall.h \
linux/sparc64/rt_sigframe.h \
linux/sparc64/set_error.c \
linux/sparc64/set_scno.c \
linux/tile/ioctls_arch1.h \
linux/tile/ioctls_inc0.h \
linux/tile/ioctls_inc1.h \
+ linux/tile/raw_syscall.h \
linux/tile/rt_sigframe.h \
linux/tile/set_error.c \
linux/tile/set_scno.c \
linux/x32/ioctls_arch1.h \
linux/x32/ioctls_inc0.h \
linux/x32/ioctls_inc1.h \
+ linux/x32/raw_syscall.h \
linux/x32/rt_sigframe.h \
linux/x32/set_error.c \
linux/x32/set_scno.c \
linux/x86_64/ioctls_inc0.h \
linux/x86_64/ioctls_inc1.h \
linux/x86_64/ioctls_inc2.h \
+ linux/x86_64/raw_syscall.h \
linux/x86_64/rt_sigframe.h \
linux/x86_64/set_error.c \
linux/x86_64/set_scno.c \
linux/xtensa/get_syscall_result.c \
linux/xtensa/ioctls_arch0.h \
linux/xtensa/ioctls_inc0.h \
+ linux/xtensa/raw_syscall.h \
linux/xtensa/set_error.c \
linux/xtensa/set_scno.c \
linux/xtensa/syscallent.h \
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t x8 __asm__("x8") = nr;
+ register kernel_ulong_t x0 __asm__("x0");
+ __asm__ __volatile__("svc 0"
+ : "=r"(x0)
+ : "r"(x8)
+ : "memory");
+ return x0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ kernel_ulong_t sc_0 = nr;
+ register kernel_ulong_t sc_19 __asm__("$19");
+ __asm__ __volatile__("callsys"
+ : "+v"(sc_0), "=r"(sc_19)
+ :
+ : "memory", "$1", "$2", "$3", "$4", "$5", "$6",
+ "$7", "$8", "$16", "$17", "$18", "$20", "$21",
+ "$22", "$23", "$24", "$25", "$27", "$28");
+ *err = sc_19;
+ return sc_0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r8 __asm__("r8") = nr;
+ register kernel_ulong_t r0 __asm__("r0");
+
+# ifdef __A7__
+# define ARC_TRAP_INSN "trap0"
+# elif defined __HS__
+# define ARC_TRAP_INSN "trap_s 0 "
+# else
+# error unrecognized arc
+# endif
+
+ __asm__ __volatile__(ARC_TRAP_INSN
+ : "=r"(r0)
+ : "r"(r8)
+ : "memory");
+
+# undef ARC_TRAP_INSN
+
+ return r0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r7 __asm__("r7") = nr;
+ register kernel_ulong_t r0 __asm__("r0");
+ __asm__ __volatile__("swi 0x0"
+ : "=r"(r0)
+ : "r"(r7)
+ : "memory");
+ return r0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r8 __asm__("r8") = nr;
+ register kernel_ulong_t r12 __asm__("r12");
+ __asm__ __volatile__("scall"
+ : "=r"(r12)
+ : "r"(r8)
+ : "memory", "cc");
+ return r12;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t ret;
+ __asm__ __volatile__("excpt 0"
+ : "=q0"(ret)
+ : "qA"(nr)
+ : "memory", "cc");
+ return ret;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r28 __asm__("r28");
+ __asm__ __volatile__("copy %%r19, %%r4\n\t"
+ "ble 0x100(%%sr2, %%r0)\n\t"
+ "copy %1, %%r20\n\t"
+ "copy %%r4, %%r19\n\t"
+ : "=r"(r28)
+ : "r"(nr)
+ : "memory", "%r1", "%r2", "%r4",
+ "%r21", "%r22", "%r23", "%r24", "%r25", "%r26" );
+ return r28;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ kernel_ulong_t ret;
+ __asm__ __volatile__("int $0x80"
+ : "=a"(ret)
+ : "a"(nr)
+ : "memory", "cc");
+ return ret;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ register kernel_ulong_t r15 __asm__("r15") = nr;
+ register kernel_ulong_t r8 __asm__("r8");
+ register kernel_ulong_t r10 __asm__("r10");
+ __asm__ __volatile__("break 0x100000"
+ : "=r"(r8), "=r"(r10), "+r"(r15)
+ :
+ : "memory", "out0", "out1", "out2",
+ "out3", "out4", "out5", "out6", "out7",
+ "r2", "r3", "r9", "r11", "r12", "r13",
+ "r14", "r16", "r17", "r18", "r19", "r20",
+ "r21", "r22", "r23", "r24", "r25", "r26",
+ "r27", "r28", "r29", "r30", "r31",
+ "p6", "p7", "p8", "p9", "p10",
+ "p11", "p12", "p13", "p14", "p15",
+ "f6", "f7", "f8", "f9", "f10",
+ "f11", "f12", "f13", "f14", "f15",
+ "f5", "f6", "f7", "f8", "f9", "f10", "f11",
+ "b6", "b7");
+ *err = !!r10;
+ return r8;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t d0 __asm__("%d0") = nr;
+ __asm__ __volatile__("trap #0"
+ : "=d"(d0)
+ : "0"(d0)
+ : "memory");
+ return d0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t num __asm__("D1Re0") = nr;
+ register kernel_ulong_t ret __asm__("D0Re0");
+ __asm__ __volatile__("SWITCH #0x440001"
+ : "=r"(ret)
+ : "d"(num)
+ : "memory");
+ return ret;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r12 __asm__("r12") = nr;
+ register kernel_ulong_t r3 __asm__("r3");
+ __asm__ __volatile__("brki r14, 8"
+ : "=r"(r3)
+ : "r"(r12)
+ : "memory", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11");
+ return r3;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ register kernel_ulong_t s0 __asm__("$16") = nr;
+ register kernel_ulong_t v0 __asm__("$2");
+ register kernel_ulong_t a3 __asm__("$7");
+ __asm__ __volatile__(".set noreorder\n\t"
+ "move %0, %2\n\t"
+ "syscall\n\t"
+ ".set reorder"
+ : "=r"(v0), "=r"(a3)
+ : "r"(s0)
+ : "memory", "hi", "lo", "$1", "$3", "$8", "$9",
+ "$10", "$11", "$12", "$13", "$14", "$15",
+ "$24", "$25");
+ *err = a3;
+ return v0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ register kernel_ulong_t r2 __asm__("r2") = nr;
+ register kernel_ulong_t r7 __asm__("r7");
+ __asm__ __volatile__("trap"
+ : "+r"(r2), "=r"(r7)
+ :
+ : "memory");
+ *err = r7;
+ return r2;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r11 __asm__("r11") = nr;
+ __asm__ __volatile__("l.sys 1"
+ : "+r"(r11)
+ :
+ : "memory", "r3", "r4", "r5", "r6", "r7", "r8",
+ "r12", "r13", "r15", "r17", "r19", "r21",
+ "r23", "r25", "r27", "r29", "r31");
+ return r11;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ register kernel_ulong_t r0 __asm__("r0") = nr;
+ register kernel_ulong_t r3 __asm__("r3");
+ __asm__ __volatile__("sc\n\t"
+ "mfcr %0"
+ : "+r"(r0), "=r"(r3)
+ :
+ : "memory", "cr0", "ctr", "lr",
+ "r4", "r5", "r6", "r7", "r8",
+ "r9", "r10", "r11", "r12");
+ *err = !!(r0 & 0x10000000);
+ return r3;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+#include "powerpc/raw_syscall.h"
--- /dev/null
+/* nothing */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t a7 __asm__("a7") = nr;
+ register kernel_ulong_t a0 __asm__("a0");
+ __asm__ __volatile__("scall"
+ : "=r"(a0)
+ : "r"(a7)
+ : "memory");
+ return a0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r1 __asm__("r1") = nr;
+ register kernel_ulong_t r2 __asm__("r2");
+ __asm__ __volatile__("svc 0"
+ : "=r"(r2)
+ : "r"(r1)
+ : "memory");
+ return r2;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+#include "s390/raw_syscall.h"
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t r3 __asm__("%r3") = nr;
+ register kernel_ulong_t r0 __asm__("%r0");
+ __asm__ __volatile__("trapa #0x10\n\t"
+ "or r0,r0\n\t"
+ "or r0,r0\n\t"
+ "or r0,r0\n\t"
+ "or r0,r0\n\t"
+ "or r0,r0\n\t"
+ : "=r"(r0)
+ : "r"(r3)
+ : "memory", "t");
+ return r0;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+#include "sh/raw_syscall.h"
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ register kernel_ulong_t g1 __asm__("g1") = nr;
+ register kernel_ulong_t rval __asm__("o0");
+ __asm__ __volatile__("ta 0x10\n\t"
+ "bcc 1f\n\t"
+ "mov 0, %0\n\t"
+ "mov 1, %0\n\t"
+ "1:"
+ : "+r"(g1), "=r"(rval)
+ :
+ : "memory", "cc", "f0", "f1", "f2", "f3", "f4",
+ "f5", "f6", "f7", "f8", "f9", "f10", "f11",
+ "f12", "f13", "f14", "f15", "f16", "f17",
+ "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29",
+ "f30", "f31");
+ *err = g1;
+ return rval;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ register kernel_ulong_t g1 __asm__("g1") = nr;
+ register kernel_ulong_t rval __asm__("o0");
+ __asm__ __volatile__("ta 0x6d\n\t"
+ "bcc,pt %%xcc, 1f\n\t"
+ "mov 0, %0\n\t"
+ "mov 1, %0\n\t"
+ "1:"
+ : "+r"(g1), "=r"(rval)
+ :
+ : "memory", "cc", "f0", "f1", "f2", "f3", "f4",
+ "f5", "f6", "f7", "f8", "f9", "f10", "f11",
+ "f12", "f13", "f14", "f15", "f16", "f17",
+ "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29",
+ "f30", "f31", "f32", "f34", "f36", "f38",
+ "f40", "f42", "f44", "f46", "f48", "f50",
+ "f52", "f54", "f56", "f58", "f60", "f62");
+ *err = g1;
+ return rval;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ kernel_ulong_t r, e, c2, c3, c4, c5, c10;
+ __asm__ __volatile__("swint1"
+ : "=R00"(r), "=R01"(e),
+ "=R02"(c2), "=R03"(c3), "=R04"(c4),
+ "=R05"(c5), "=R10"(c10)
+ : "R10"(nr)
+ : "memory", "r6", "r7", "r8", "r9", "r11",
+ "r12", "r13", "r14", "r15", "r16", "r17",
+ "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29");
+ *err = e;
+ return r;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+#include "x86_64/raw_syscall.h"
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ kernel_ulong_t ret;
+ __asm__ __volatile__("syscall"
+ : "=a"(ret)
+ : "a"(nr)
+ : "memory", "cc", "rcx", "r11");
+ return ret;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
--- /dev/null
+/*
+ * Raw syscalls.
+ *
+ * Copyright (c) 2018 The strace developers.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STRACE_RAW_SYSCALL_H
+#define STRACE_RAW_SYSCALL_H
+
+# include "kernel_types.h"
+
+static inline kernel_ulong_t
+raw_syscall_0(const kernel_ulong_t nr, kernel_ulong_t *err)
+{
+ *err = 0;
+ register kernel_ulong_t a2 __asm__("a2") = nr;
+ __asm__ __volatile__("syscall"
+ : "=a"(a2)
+ : "r"(a2)
+ : "memory");
+ return a2;
+}
+# define raw_syscall_0 raw_syscall_0
+
+#endif /* !STRACE_RAW_SYSCALL_H */
projects / strace / commitdiff