In HexagonISelLowering, there is code to handle the case when
a function returns an i1 type. In this case, we need to generate
extra nodes to copy the result from R0 to a predicate register.
The code was returning the wrong value for the chain edge which
caused an assert "Wrong topological sorting" when converting the
instructions to MIs.
This patch fixes the problem by returning the chain for the final
copy.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316367
91177308-0d34-0410-b5e6-
96231b3b80d8
// as an implicit def to the call (EmitMachineNode).
RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
Glue = TPR.getValue(1);
+ Chain = TPR.getValue(0);
} else {
RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
RVLocs[i].getValVT(), Glue);
Glue = RetVal.getValue(2);
+ Chain = RetVal.getValue(1);
}
InVals.push_back(RetVal.getValue(0));
- Chain = RetVal.getValue(1);
}
return Chain;
--- /dev/null
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+; Test that the compiler does not assert because the DAG is not correct.
+; CHECK: call foo
+
+%returntype = type { i1, i32 }
+
+define i32 @test(i32* %a0, i32* %a1, i32* %a2) #0 {
+b3:
+ br i1 undef, label %b6, label %b4
+
+b4: ; preds = %b3
+ %v5 = call %returntype @foo(i32* nonnull undef, i32* %a2, i32* %a0) #0
+ ret i32 1
+
+b6: ; preds = %b3
+ unreachable
+}
+
+declare %returntype @foo(i32*, i32*, i32*) #0
+
+attributes #0 = { nounwind }