]> granicus.if.org Git - llvm/commitdiff
[InstCombine] simplify dyn_cast + isa; NFCI
authorSanjay Patel <spatel@rotateright.com>
Mon, 6 Feb 2017 17:16:16 +0000 (17:16 +0000)
committerSanjay Patel <spatel@rotateright.com>
Mon, 6 Feb 2017 17:16:16 +0000 (17:16 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294198 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Transforms/InstCombine/InstructionCombining.cpp

index b74b3273acd764ac04211edb66e32106824264e9..ba65ea6f510ad324915bd802d2769149dcb9b324 100644 (file)
@@ -568,13 +568,11 @@ static Value *tryFactorization(InstCombiner::BuilderTy *Builder,
         if (isa<OverflowingBinaryOperator>(&I))
           HasNSW = I.hasNoSignedWrap();
 
-        if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS))
-          if (isa<OverflowingBinaryOperator>(Op0))
-            HasNSW &= Op0->hasNoSignedWrap();
+        if (auto *LOBO = dyn_cast<OverflowingBinaryOperator>(LHS))
+          HasNSW &= LOBO->hasNoSignedWrap();
 
-        if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
-          if (isa<OverflowingBinaryOperator>(Op1))
-            HasNSW &= Op1->hasNoSignedWrap();
+        if (auto *ROBO = dyn_cast<OverflowingBinaryOperator>(RHS))
+          HasNSW &= ROBO->hasNoSignedWrap();
 
         // We can propagate 'nsw' if we know that
         //  %Y = mul nsw i16 %X, C