[AVX-512] Teach the disassembler about all of the EVEX gather and scatter instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292094 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/Disassembler/X86Disassembler.cpp b/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 91849945e10623e66a77f6af5b53e908c2180e2b..54fd2afd353c7d33ee7728f4d197079441345fe1 100644 (file)
--- a/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -767,7 +767,27 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
                        Opcode == X86::VPGATHERDQYrm ||
                        Opcode == X86::VPGATHERQQrm ||
                        Opcode == X86::VPGATHERDDrm ||
-                       Opcode == X86::VPGATHERQDrm);
+                       Opcode == X86::VPGATHERQDrm ||
+                       Opcode == X86::VGATHERDPDZ128rm ||
+                       Opcode == X86::VGATHERDPDZ256rm ||
+                       Opcode == X86::VGATHERDPSZ128rm ||
+                       Opcode == X86::VGATHERQPDZ128rm ||
+                       Opcode == X86::VGATHERQPSZ128rm ||
+                       Opcode == X86::VPGATHERDDZ128rm ||
+                       Opcode == X86::VPGATHERDQZ128rm ||
+                       Opcode == X86::VPGATHERDQZ256rm ||
+                       Opcode == X86::VPGATHERQDZ128rm ||
+                       Opcode == X86::VPGATHERQQZ128rm ||
+                       Opcode == X86::VSCATTERDPDZ128mr ||
+                       Opcode == X86::VSCATTERDPDZ256mr ||
+                       Opcode == X86::VSCATTERDPSZ128mr ||
+                       Opcode == X86::VSCATTERQPDZ128mr ||
+                       Opcode == X86::VSCATTERQPSZ128mr ||
+                       Opcode == X86::VPSCATTERDDZ128mr ||
+                       Opcode == X86::VPSCATTERDQZ128mr ||
+                       Opcode == X86::VPSCATTERDQZ256mr ||
+                       Opcode == X86::VPSCATTERQDZ128mr ||
+                       Opcode == X86::VPSCATTERQQZ128mr);
     bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
                        Opcode == X86::VGATHERDPSYrm ||
                        Opcode == X86::VGATHERQPSYrm ||
@@ -775,13 +795,49 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
                        Opcode == X86::VPGATHERDQZrm ||
                        Opcode == X86::VPGATHERQQYrm ||
                        Opcode == X86::VPGATHERDDYrm ||
-                       Opcode == X86::VPGATHERQDYrm);
+                       Opcode == X86::VPGATHERQDYrm ||
+                       Opcode == X86::VGATHERDPSZ256rm ||
+                       Opcode == X86::VGATHERQPDZ256rm ||
+                       Opcode == X86::VGATHERQPSZ256rm ||
+                       Opcode == X86::VPGATHERDDZ256rm ||
+                       Opcode == X86::VPGATHERQQZ256rm ||
+                       Opcode == X86::VPGATHERQDZ256rm ||
+                       Opcode == X86::VSCATTERDPDZmr ||
+                       Opcode == X86::VPSCATTERDQZmr ||
+                       Opcode == X86::VSCATTERDPSZ256mr ||
+                       Opcode == X86::VSCATTERQPDZ256mr ||
+                       Opcode == X86::VSCATTERQPSZ256mr ||
+                       Opcode == X86::VPSCATTERDDZ256mr ||
+                       Opcode == X86::VPSCATTERQQZ256mr ||
+                       Opcode == X86::VPSCATTERQDZ256mr ||
+                       Opcode == X86::VGATHERPF0DPDm ||
+                       Opcode == X86::VGATHERPF1DPDm ||
+                       Opcode == X86::VSCATTERPF0DPDm ||
+                       Opcode == X86::VSCATTERPF1DPDm);
     bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
                        Opcode == X86::VGATHERDPSZrm ||
                        Opcode == X86::VGATHERQPSZrm ||
                        Opcode == X86::VPGATHERQQZrm ||
                        Opcode == X86::VPGATHERDDZrm ||
-                       Opcode == X86::VPGATHERQDZrm);
+                       Opcode == X86::VPGATHERQDZrm ||
+                       Opcode == X86::VSCATTERQPDZmr ||
+                       Opcode == X86::VSCATTERDPSZmr ||
+                       Opcode == X86::VSCATTERQPSZmr ||
+                       Opcode == X86::VPSCATTERQQZmr ||
+                       Opcode == X86::VPSCATTERDDZmr ||
+                       Opcode == X86::VPSCATTERQDZmr ||
+                       Opcode == X86::VGATHERPF0DPSm ||
+                       Opcode == X86::VGATHERPF0QPDm ||
+                       Opcode == X86::VGATHERPF0QPSm ||
+                       Opcode == X86::VGATHERPF1DPSm ||
+                       Opcode == X86::VGATHERPF1QPDm ||
+                       Opcode == X86::VGATHERPF1QPSm ||
+                       Opcode == X86::VSCATTERPF0DPSm ||
+                       Opcode == X86::VSCATTERPF0QPDm ||
+                       Opcode == X86::VSCATTERPF0QPSm ||
+                       Opcode == X86::VSCATTERPF1DPSm ||
+                       Opcode == X86::VSCATTERPF1QPDm ||
+                       Opcode == X86::VSCATTERPF1QPSm);
     if (IndexIs128 || IndexIs256 || IndexIs512) {
       unsigned IndexOffset = insn.sibIndex -
                          (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);

diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
index 05ec2ef5eb0becbed92a99e02ee68d081f61a430..d3919d5b695ae5d81c397a6ae9c18311d66d6451 100644 (file)
--- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
+++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
@@ -1758,7 +1758,14 @@ static int readOperands(struct InternalInstruction* insn) {
       // VSIB can use the V2 bit so check only the other bits.
       if (needVVVV)
         needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
-      // fallthrough
+      if (readModRM(insn))
+        return -1;
+      if (fixupReg(insn, &Op))
+        return -1;
+      // Apply the AVX512 compressed displacement scaling factor.
+      if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
+        insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
+      break;
     case ENCODING_REG:
     CASE_ENCODING_RM:
       if (readModRM(insn))

diff --git a/test/MC/Disassembler/X86/avx-512.txt b/test/MC/Disassembler/X86/avx-512.txt
index fd1db3b22ec55233679e3cd041711e773c454f74..b0d1009476f50369707db78cae73dd5dafa2595c 100644 (file)
--- a/test/MC/Disassembler/X86/avx-512.txt
+++ b/test/MC/Disassembler/X86/avx-512.txt
@@ -170,3 +170,98 @@
 # CHECK: vcmpps        $127, %xmm27, %xmm11, %k4
 0x62 0x91 0x24 0x08 0xc2 0xe3 0x7f
 
+# CHECK: vpgatherdd 256(%r9,%xmm31), %xmm17 {%k1}
+0x62 0x82 0x7d 0x01 0x90 0x4c 0x39 0x40
+
+# CHECK: vpgatherdd 256(%r9,%ymm31), %ymm19 {%k1}
+0x62 0x82 0x7d 0x21 0x90 0x5c 0x39 0x40
+
+# CHECK: vpgatherdq 256(%r9,%xmm31), %xmm17 {%k1}
+0x62 0x82 0xfd 0x01 0x90 0x4c 0x39 0x20
+
+# CHECK: vpgatherdq 256(%r9,%xmm31), %ymm26 {%k1}
+0x62 0x02 0xfd 0x21 0x90 0x54 0x39 0x20
+
+# CHECK: vpgatherqd 256(%r9,%xmm31), %xmm21 {%k1}
+0x62 0x82 0x7d 0x01 0x91 0x6c 0x39 0x40
+
+# CHECK: vpgatherqd 256(%r9,%ymm31), %xmm25 {%k1}
+0x62 0x02 0x7d 0x21 0x91 0x4c 0x39 0x40
+
+# CHECK: vpgatherqq 256(%r9,%xmm31), %xmm18 {%k1}
+0x62 0x82 0xfd 0x01 0x91 0x54 0x39 0x20
+
+# CHECK: vpgatherqq 256(%r9,%ymm31), %ymm19 {%k1}
+0x62 0x82 0xfd 0x21 0x91 0x5c 0x39 0x20
+
+# CHECK: vgatherdpd 256(%r9,%xmm31), %xmm17 {%k1}
+0x62 0x82 0xfd 0x01 0x92 0x4c 0x39 0x20
+
+# CHECK: vgatherdpd 256(%r9,%xmm31), %ymm23 {%k1}
+0x62 0x82 0xfd 0x21 0x92 0x7c 0x39 0x20
+
+# CHECK: vgatherdps 256(%r9,%xmm31), %xmm18 {%k1}
+0x62 0x82 0x7d 0x01 0x92 0x54 0x39 0x40
+
+# CHECK: vgatherdps 256(%r9,%ymm31), %ymm27 {%k1}
+0x62 0x02 0x7d 0x21 0x92 0x5c 0x39 0x40
+
+# CHECK: vgatherqpd 256(%r9,%xmm31), %xmm17 {%k1}
+0x62 0x82 0xfd 0x01 0x93 0x4c 0x39 0x20
+
+# CHECK: vgatherqpd 256(%r9,%ymm31), %ymm29 {%k1}
+0x62 0x02 0xfd 0x21 0x93 0x6c 0x39 0x20
+
+# CHECK: vgatherqps 256(%r9,%xmm31), %xmm21 {%k1}
+0x62 0x82 0x7d 0x01 0x93 0x6c 0x39 0x40
+
+# CHECK: vgatherqps 256(%r9,%ymm31), %xmm19 {%k1}
+0x62 0x82 0x7d 0x21 0x93 0x5c 0x39 0x40
+
+# CHECK: vpscatterdd %xmm20, 256(%r9,%xmm31) {%k1}
+0x62 0x82 0x7d 0x01 0xa0 0x64 0x39 0x40
+
+# CHECK: vpscatterdd %ymm28, 256(%r9,%ymm31) {%k1}
+0x62 0x02 0x7d 0x21 0xa0 0x64 0x39 0x40
+
+# CHECK: vpscatterdq %xmm21, 256(%r9,%xmm31) {%k1}
+0x62 0x82 0xfd 0x01 0xa0 0x6c 0x39 0x20
+
+# CHECK: vpscatterdq %ymm28, 256(%r9,%xmm31) {%k1}
+0x62 0x02 0xfd 0x21 0xa0 0x64 0x39 0x20
+
+# CHECK: vpscatterqd %xmm22, 256(%r9,%xmm31) {%k1}
+0x62 0x82 0x7d 0x01 0xa1 0x74 0x39 0x40
+
+# CHECK: vpscatterqd %xmm24, 256(%r9,%ymm31) {%k1}
+0x62 0x02 0x7d 0x21 0xa1 0x44 0x39 0x40
+
+# CHECK: vpscatterqq %xmm28, 256(%r9,%xmm31) {%k1}
+0x62 0x02 0xfd 0x01 0xa1 0x64 0x39 0x20
+
+# CHECK: vpscatterqq %ymm19, 256(%r9,%ymm31) {%k1}
+0x62 0x82 0xfd 0x21 0xa1 0x5c 0x39 0x20
+
+# CHECK: vscatterdps %xmm20, 256(%r9,%xmm31) {%k1}
+0x62 0x82 0x7d 0x01 0xa2 0x64 0x39 0x40
+
+# CHECK: vscatterdps %ymm28, 256(%r9,%ymm31) {%k1}
+0x62 0x02 0x7d 0x21 0xa2 0x64 0x39 0x40
+
+# CHECK: vscatterdpd %xmm21, 256(%r9,%xmm31) {%k1}
+0x62 0x82 0xfd 0x01 0xa2 0x6c 0x39 0x20
+
+# CHECK: vscatterdpd %ymm28, 256(%r9,%xmm31) {%k1}
+0x62 0x02 0xfd 0x21 0xa2 0x64 0x39 0x20
+
+# CHECK: vscatterqps %xmm22, 256(%r9,%xmm31) {%k1}
+0x62 0x82 0x7d 0x01 0xa3 0x74 0x39 0x40
+
+# CHECK: vscatterqps %xmm24, 256(%r9,%ymm31) {%k1}
+0x62 0x02 0x7d 0x21 0xa3 0x44 0x39 0x40
+
+# CHECK: vscatterqpd %xmm28, 256(%r9,%xmm31) {%k1}
+0x62 0x02 0xfd 0x01 0xa3 0x64 0x39 0x20
+
+# CHECK: vscatterqpd %ymm19, 256(%r9,%ymm31) {%k1}
+0x62 0x82 0xfd 0x21 0xa3 0x5c 0x39 0x20