soc: release interrupts which are not reserved by timers any more

diff --git a/components/esp32/intr_alloc.c b/components/esp32/intr_alloc.c
index 534354cdc5100ccdb03854091f550437a185dc6d..c51b348c9895d237e60910008f22c2d1baf6c21f 100644 (file)
--- a/components/esp32/intr_alloc.c
+++ b/components/esp32/intr_alloc.c
@@ -100,8 +100,8 @@ const static int_desc_t int_desc[32]={
     { 1, INTTP_NA,    {INT6RES,        INT6RES       } }, //6
     { 1, INTTP_NA,    {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //7
     { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //8
-    { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //9 //FRC1
-    { 1, INTTP_EDGE , {INTDESC_RESVD,  INTDESC_RESVD } }, //10 //FRC2
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //9
+    { 1, INTTP_EDGE , {INTDESC_NORMAL, INTDESC_NORMAL} }, //10
     { 3, INTTP_NA,    {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //11
     { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //12
     { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //13

diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h
index 3b1e85f2f9b216821edc35b13ddda2f83d68116b..67a6a1c0573a72427b18129d9c7fa6baad4cfda1 100644 (file)
--- a/components/soc/esp32/include/soc/soc.h
+++ b/components/soc/esp32/include/soc/soc.h
@@ -376,7 +376,7 @@
  *      7                       1               software                BT/BLE VHCI             BT/BLE VHCI
  *      8                       1               extern level            BT/BLE BB(RX/TX)        BT/BLE BB(RX/TX)
  *      9                       1               extern level
- *      10                      1               extern edge             Internal Timer
+ *      10                      1               extern edge
  *      11                      3               profiling
  *      12                      1               extern level
  *      13                      1               extern level
@@ -388,7 +388,7 @@
  *      19                      2               extern level
  *      20                      2               extern level
  *      21                      2               extern level
- *      22                      3               extern edge             FRC1 timer
+ *      22                      3               extern edge
  *      23                      3               extern level
  *      24                      4               extern level            TG1_WDT
  *      25                      4               extern level            CACHEERR