]> granicus.if.org Git - llvm/commitdiff
[X86] Add missing predicate to a pattern. NFC
authorCraig Topper <craig.topper@intel.com>
Sun, 5 Nov 2017 21:14:06 +0000 (21:14 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 5 Nov 2017 21:14:06 +0000 (21:14 +0000)
Other patterns had higher priority so this wasn't noticed. But we shouldn't be dependent on pattern order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317442 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrAVX512.td

index ae56349580a7cdd7a77252a7077276628bd2b7e4..11274d988d2d770812aa8a531cfcb81581aa1e23 100644 (file)
@@ -7618,6 +7618,7 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
   }
   }
 
+let Predicates = [HasAVX512] in {
   def : Pat<(_.EltVT (OpNode _.FRC:$src)),
             (!cast<Instruction>(NAME#SUFF#Zr)
                 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
@@ -7626,6 +7627,7 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
             (!cast<Instruction>(NAME#SUFF#Zm)
                 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512, OptForSize]>;
 }
+}
 
 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
   defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,