"src/bootloader_clock.c"
"src/bootloader_common.c"
"src/bootloader_flash.c"
+ "src/bootloader_flash_config.c"
"src/bootloader_random.c"
"src/bootloader_utility.c"
"src/esp_image_format.c"
*/
void bootloader_common_vddsdio_configure();
-/**
- * @brief Set the flash CS setup and hold time.
- *
- * CS setup time is recomemded to be 1.5T, and CS hold time is recommended to be 2.5T.
- * cs_setup = 1, cs_setup_time = 0; cs_hold = 1, cs_hold_time = 1
- */
-void bootloader_common_set_flash_cs_timing();
-
#ifdef __cplusplus
}
#endif
--- /dev/null
+// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "esp_image_format.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Update the flash id in g_rom_flashchip(global esp_rom_spiflash_chip_t structure).
+ *
+ * @return None
+ */
+void bootloader_flash_update_id();
+
+/**
+ * @brief Set the flash CS setup and hold time.
+ *
+ * @note CS setup time is recomemded to be 1.5T, and CS hold time is recommended to be 2.5T.
+ * cs_setup = 1, cs_setup_time = 0; cs_hold = 1, cs_hold_time = 1.
+ *
+ * @return None
+ */
+void bootloader_flash_cs_timing_config();
+
+/**
+ * @brief Configure SPI flash clock.
+ *
+ * @note This function only set clock frequency for SPI0.
+ *
+ * @param pfhdr Pointer to App image header, from where to fetch flash settings.
+ *
+ * @return None
+ */
+void bootloader_flash_clock_config(const esp_image_header_t* pfhdr);
+
+/**
+ * @brief Configure SPI flash gpio, include the IO matrix and drive strength configuration.
+ *
+ * @param pfhdr Pointer to App image header, from where to fetch flash settings.
+ *
+ * @return None
+ */
+void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr);
+
+/**
+ * @brief Configure SPI flash read dummy based on different mode and frequency.
+ *
+ * @param pfhdr Pointer to App image header, from where to fetch flash settings.
+ *
+ * @return None
+ */
+void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr);
+
+#ifdef __cplusplus
+}
+#endif
#include "bootloader_common.h"
#include "soc/gpio_periph.h"
#include "soc/rtc.h"
-#include "soc/efuse_reg.h"
-#include "soc/spi_reg.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
#include "sys/param.h"
}
#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
}
-
-void bootloader_common_set_flash_cs_timing()
-{
- SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
- SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
- SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
- SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
- SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
- SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
-}
--- /dev/null
+// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp32/rom/gpio.h"
+#include "esp32/rom/spi_flash.h"
+#include "esp32/rom/efuse.h"
+#include "soc/gpio_periph.h"
+#include "soc/efuse_reg.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+
+void bootloader_flash_update_id()
+{
+ g_rom_flashchip.device_id = bootloader_read_flash_id();
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+ SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
+ SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
+ SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
+ SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
+ SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
+ SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
+{
+ uint32_t spi_clk_div = 0;
+ switch (pfhdr->spi_speed) {
+ case ESP_IMAGE_SPI_SPEED_80M:
+ spi_clk_div = 1;
+ break;
+ case ESP_IMAGE_SPI_SPEED_40M:
+ spi_clk_div = 2;
+ break;
+ case ESP_IMAGE_SPI_SPEED_26M:
+ spi_clk_div = 3;
+ break;
+ case ESP_IMAGE_SPI_SPEED_20M:
+ spi_clk_div = 4;
+ break;
+ default:
+ break;
+ }
+ esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
+{
+ uint32_t drv = 2;
+ if (pfhdr->spi_speed == ESP_IMAGE_SPI_SPEED_80M) {
+ drv = 3;
+ }
+
+ uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
+ uint32_t pkg_ver = chip_ver & 0x7;
+
+ if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
+ // For ESP32D2WD the SPI pins are already configured
+ // flash clock signal should come from IO MUX.
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+ } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
+ // For ESP32PICOD2 the SPI pins are already configured
+ // flash clock signal should come from IO MUX.
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+ } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
+ // For ESP32PICOD4 the SPI pins are already configured
+ // flash clock signal should come from IO MUX.
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+ } else {
+ const uint32_t spiconfig = ets_efuse_get_spiconfig();
+ if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
+ gpio_matrix_out(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
+ gpio_matrix_out(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
+ gpio_matrix_in(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
+ gpio_matrix_out(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
+ gpio_matrix_in(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
+ gpio_matrix_out(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
+ gpio_matrix_in(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
+ gpio_matrix_out(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
+ gpio_matrix_in(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
+ //select pin function gpio
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
+ // flash clock signal should come from IO MUX.
+ // set drive ability for clock
+ PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+
+ uint32_t flash_id = g_rom_flashchip.device_id;
+ if (flash_id == FLASH_ID_GD25LQ32C) {
+ // Set drive ability for 1.8v flash in 80Mhz.
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
+ SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
+ }
+ }
+ }
+}
+
+void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
+{
+ int spi_cache_dummy = 0;
+ uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
+ if (modebit & SPI_FASTRD_MODE) {
+ if (modebit & SPI_FREAD_QIO) { //SPI mode is QIO
+ spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
+ } else if (modebit & SPI_FREAD_DIO) { //SPI mode is DIO
+ spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
+ SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
+ } else if(modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) { //SPI mode is QOUT or DIO
+ spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
+ }
+ }
+
+ extern uint8_t g_rom_spiflash_dummy_len_plus[];
+ switch (pfhdr->spi_speed) {
+ case ESP_IMAGE_SPI_SPEED_80M:
+ g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
+ g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
+ break;
+ case ESP_IMAGE_SPI_SPEED_40M:
+ g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
+ g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
+ break;
+ case ESP_IMAGE_SPI_SPEED_26M:
+ case ESP_IMAGE_SPI_SPEED_20M:
+ g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
+ g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
+ break;
+ default:
+ break;
+ }
+
+ SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
+ SPI_USR_DUMMY_CYCLELEN_S);
+}
\ No newline at end of file
#include "bootloader_config.h"
#include "bootloader_clock.h"
#include "bootloader_common.h"
+#include "bootloader_flash_config.h"
#include "flash_qio_mode.h"
static esp_err_t bootloader_main();
static void print_flash_info(const esp_image_header_t* pfhdr);
static void update_flash_config(const esp_image_header_t* pfhdr);
-static void flash_gpio_configure(const esp_image_header_t* pfhdr);
+static void bootloader_init_flash_configure(const esp_image_header_t* pfhdr);
static void uart_console_configure(void);
static void wdt_reset_check(void);
ESP_LOGE(TAG, "failed to load bootloader header!");
return ESP_FAIL;
}
- flash_gpio_configure(&fhdr);
+ bootloader_init_flash_configure(&fhdr);
#if (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240)
//Check if ESP32 is rated for a CPU frequency of 160MHz only
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
#endif
}
-#define FLASH_CLK_IO 6
-#define FLASH_CS_IO 11
-#define FLASH_SPIQ_IO 7
-#define FLASH_SPID_IO 8
-#define FLASH_SPIWP_IO 10
-#define FLASH_SPIHD_IO 9
-#define FLASH_IO_MATRIX_DUMMY_40M 1
-#define FLASH_IO_MATRIX_DUMMY_80M 2
-#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
-
/*
* Bootloader reads SPI configuration from bin header, so that
* the burning configuration can be different with compiling configuration.
*/
-static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
+static void IRAM_ATTR bootloader_init_flash_configure(const esp_image_header_t* pfhdr)
{
- int spi_cache_dummy = 0;
- int drv = 2;
- switch (pfhdr->spi_mode) {
- case ESP_IMAGE_SPI_MODE_QIO:
- spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
- break;
- case ESP_IMAGE_SPI_MODE_DIO:
- spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
- SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
- break;
- case ESP_IMAGE_SPI_MODE_QOUT:
- case ESP_IMAGE_SPI_MODE_DOUT:
- default:
- spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
- break;
- }
-
- /* dummy_len_plus values defined in ROM for SPI flash configuration */
- extern uint8_t g_rom_spiflash_dummy_len_plus[];
- switch (pfhdr->spi_speed) {
- case ESP_IMAGE_SPI_SPEED_80M:
- g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
- g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
- SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
- SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
- drv = 3;
- break;
- case ESP_IMAGE_SPI_SPEED_40M:
- g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
- g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
- SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
- SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
- break;
- case ESP_IMAGE_SPI_SPEED_26M:
- case ESP_IMAGE_SPI_SPEED_20M:
- SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
- break;
- default:
- break;
- }
-
- uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
- uint32_t pkg_ver = chip_ver & 0x7;
-
- if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
- // For ESP32D2WD the SPI pins are already configured
- // flash clock signal should come from IO MUX.
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
- } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
- // For ESP32PICOD2 the SPI pins are already configured
- // flash clock signal should come from IO MUX.
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
- } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
- // For ESP32PICOD4 the SPI pins are already configured
- // flash clock signal should come from IO MUX.
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
- } else {
- const uint32_t spiconfig = ets_efuse_get_spiconfig();
- if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
- gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
- gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
- gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
- gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
- gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
- gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
- gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
- gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
- gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
- //select pin function gpio
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
- // flash clock signal should come from IO MUX.
- // set drive ability for clock
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
-
- #if CONFIG_SPIRAM_TYPE_ESPPSRAM32
- uint32_t flash_id = g_rom_flashchip.device_id;
- if (flash_id == FLASH_ID_GD25LQ32C) {
- // Set drive ability for 1.8v flash in 80Mhz.
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
- SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
- }
- #endif
- }
- }
-
- // improve the flash cs timing.
- bootloader_common_set_flash_cs_timing();
+ bootloader_flash_gpio_config(pfhdr);
+ bootloader_flash_dummy_config(pfhdr);
+ bootloader_flash_cs_timing_config();
}
static void uart_console_configure(void)
#include "trax.h"
#include "esp_ota_ops.h"
#include "esp_efuse.h"
-#include "bootloader_common.h"
+#include "bootloader_flash_config.h"
#define STRINGIFY(s) STRINGIFY2(s)
#define STRINGIFY2(s) #s
abort();
#endif
}
-# else // If psram is uninitialized, we need to improve the flash cs timing.
- bootloader_common_set_flash_cs_timing();
#endif
ESP_EARLY_LOGI(TAG, "Pro cpu up.");
esp_coex_adapter_register(&g_coex_adapter_funcs);
#endif
+ bootloader_flash_update_id();
+#if !CONFIG_SPIRAM_BOOT_INIT // If psram is uninitialized, we need to improve some flash configuration.
+ esp_image_header_t fhdr;
+ const esp_partition_t *partition = esp_ota_get_running_partition();
+ spi_flash_read(partition->address, &fhdr, sizeof(esp_image_header_t));
+ bootloader_flash_clock_config(&fhdr);
+ bootloader_flash_gpio_config(&fhdr);
+ bootloader_flash_dummy_config(&fhdr);
+ bootloader_flash_cs_timing_config();
+#endif
+
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
ESP_TASK_MAIN_STACK, NULL,
ESP_TASK_MAIN_PRIO, NULL, 0);
#include "esp32/rom/efuse.h"
#include "soc/dport_reg.h"
#include "soc/efuse_periph.h"
+#include "soc/spi_caps.h"
#include "driver/gpio.h"
#include "driver/spi_common.h"
#include "driver/periph_ctrl.h"
// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
// hardcode the flash pins as well, making this code incompatible with either a setup
// that has the flash on non-standard pins or ESP32s with built-in flash.
-#define FLASH_CLK_IO 6
-#define FLASH_CS_IO 11
#define PSRAM_SPIQ_SD0_IO 7
#define PSRAM_SPID_SD1_IO 8
#define PSRAM_SPIWP_SD3_IO 10
#define PSRAM_INTERNAL_IO_28 28
#define PSRAM_INTERNAL_IO_29 29
-#define PSRAM_IO_MATRIX_DUMMY_40M 1
-#define PSRAM_IO_MATRIX_DUMMY_80M 2
+#define PSRAM_IO_MATRIX_DUMMY_40M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M
+#define PSRAM_IO_MATRIX_DUMMY_80M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M
#define _SPI_CACHE_PORT 0
#define _SPI_FLASH_PORT 1
gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
//select pin function gpio
- if ((psram_io->flash_clk_io == FLASH_CLK_IO) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
+ if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
//flash clock signal should come from IO MUX.
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
} else {
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
- psram_io.flash_clk_io = FLASH_CLK_IO;
- psram_io.flash_cs_io = FLASH_CS_IO;
+ psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK;
+ psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS;
psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO;
psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO;
psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO;
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
//SPI status register
-#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
-#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
-#define ESP_ROM_SPIFLASH_BP0 BIT2
-#define ESP_ROM_SPIFLASH_BP1 BIT3
-#define ESP_ROM_SPIFLASH_BP2 BIT4
-#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
-#define ESP_ROM_SPIFLASH_QE BIT9
+#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
+#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
+#define ESP_ROM_SPIFLASH_BP0 BIT2
+#define ESP_ROM_SPIFLASH_BP1 BIT3
+#define ESP_ROM_SPIFLASH_BP2 BIT4
+#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
+#define ESP_ROM_SPIFLASH_QE BIT9
+
+//Extra dummy for flash read
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
#define FLASH_ID_GD25LQ32C 0xC86016
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