[MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD

NarrowScalar G_ZEXTLOAD and G_SEXTLOAD to s32 for MIPS32.

Differential Revision: https://reviews.llvm.org/D66205

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369512 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index 247d3bfd0441fddf256a3d06cabe69e5d8379426..9ba36d4ee3249ff6a3370ad68ecb0d21431f9f28 100644 (file)
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -50,9 +50,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
      .legalFor({{s64, s32}});
 
   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
-    .legalForTypesWithMemDesc({{s32, p0, 8, 8},
-                               {s32, p0, 16, 8}})
-      .minScalar(0, s32);
+      .legalForTypesWithMemDesc({{s32, p0, 8, 8},
+                                 {s32, p0, 16, 8}})
+      .clampScalar(0, s32, s32);
 
   getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
       .legalIf([](const LegalityQuery &Query) { return false; })

diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index 51a0e6cc5afe1394e4ba76430f03ab19f885d707..25481182ad236228adb3d43c65d94029b64454b9 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -6,10 +6,12 @@
   define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
   define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
   define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
+  define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
   define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
+  define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
 
 ...
 ---
@@ -93,6 +95,32 @@ body:             |
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
+...
+---
+name:            load4_s32_to_zextLoad4_s64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[C]](s32)
+    ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
+    ; MIPS32: $v0 = COPY [[UV]](s32)
+    ; MIPS32: $v1 = COPY [[UV1]](s32)
+    ; MIPS32: RetRA implicit $v0, implicit $v1
+    %0:_(p0) = COPY $a0
+    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px)
+    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+    $v0 = COPY %3(s32)
+    $v1 = COPY %4(s32)
+    RetRA implicit $v0, implicit $v1
+
 ...
 ---
 name:            load1_s8_to_sextLoad1_s32
@@ -176,3 +204,32 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            load4_s32_to_sextLoad4_s64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
+    ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[ASHR]](s32)
+    ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
+    ; MIPS32: $v0 = COPY [[UV]](s32)
+    ; MIPS32: $v1 = COPY [[UV1]](s32)
+    ; MIPS32: RetRA implicit $v0, implicit $v1
+    %0:_(p0) = COPY $a0
+    %2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px)
+    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+    $v0 = COPY %3(s32)
+    $v1 = COPY %4(s32)
+    RetRA implicit $v0, implicit $v1
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
index 40bfc1dec0e9f4b8e0b42f3b778d1daed2fe1ed8..bc598603135436e55dd21fe0ce27af91a1930422 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
@@ -49,6 +49,19 @@ entry:
   ret i16 %conv
 }
 
+define i64 @load4_s32_to_zextLoad4_s64(i32* %px) {
+; MIPS32-LABEL: load4_s32_to_zextLoad4_s64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lw $2, 0($4)
+; MIPS32-NEXT:    ori $3, $zero, 0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %px
+  %conv = zext i32 %0 to i64
+  ret i64 %conv
+}
+
 define i32 @load1_s8_to_sextLoad1_s32(i8* %px) {
 ; MIPS32-LABEL: load1_s8_to_sextLoad1_s32:
 ; MIPS32:       # %bb.0: # %entry
@@ -96,3 +109,18 @@ entry:
   %conv = sext i8 %0 to i16
   ret i16 %conv
 }
+
+define i64 @load4_s32_to_sextLoad4_s64(i32* %px) {
+; MIPS32-LABEL: load4_s32_to_sextLoad4_s64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lw $1, 0($4)
+; MIPS32-NEXT:    ori $2, $zero, 31
+; MIPS32-NEXT:    srav $3, $1, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %px
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}

diff --git a/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir b/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
index c1c6974bf992b5c43934923fafde92cd85fdcb5f..7867a2fa2a7f60f1ae6b97f4edb93fed21c2a535 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
+++ b/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
@@ -6,10 +6,12 @@
   define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
   define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
   define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
+  define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
   define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
+  define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
 
 ...
 ---
@@ -98,6 +100,31 @@ body:             |
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
+...
+---
+name:            load4_s32_to_zextLoad4_s64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
+    ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
+    ; MIPS32: $v0 = COPY [[UV]](s32)
+    ; MIPS32: $v1 = COPY [[UV1]](s32)
+    ; MIPS32: RetRA implicit $v0, implicit $v1
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+    %2:_(s64) = G_ZEXT %1(s32)
+    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+    $v0 = COPY %3(s32)
+    $v1 = COPY %4(s32)
+    RetRA implicit $v0, implicit $v1
+
 ...
 ---
 name:            load1_s8_to_sextLoad1_s32
@@ -186,3 +213,28 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            load4_s32_to_sextLoad4_s64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
+    ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
+    ; MIPS32: $v0 = COPY [[UV]](s32)
+    ; MIPS32: $v1 = COPY [[UV1]](s32)
+    ; MIPS32: RetRA implicit $v0, implicit $v1
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+    %2:_(s64) = G_SEXT %1(s32)
+    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+    $v0 = COPY %3(s32)
+    $v1 = COPY %4(s32)
+    RetRA implicit $v0, implicit $v1
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
index eb3d174c2625c76ae93c7f22e15aff761820241f..ee77cfcea768cf61e4e76b5614e1e5f46802edf5 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
+++ b/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
@@ -4,8 +4,10 @@
 
   define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
   define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
+  define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
   define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
   define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
+  define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
 
 ...
 ---
@@ -49,6 +51,33 @@ body:             |
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
+...
+---
+name:            load4_s32_to_zextLoad4_s64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: $v1 = COPY [[C]](s32)
+    ; MIPS32: RetRA implicit $v0, implicit $v1
+    %0:_(p0) = COPY $a0
+    %5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+    %6:_(s32) = G_CONSTANT i32 0
+    %2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
+    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+    $v0 = COPY %3(s32)
+    $v1 = COPY %4(s32)
+    RetRA implicit $v0, implicit $v1
+
 ...
 ---
 name:            load1_s8_to_sextLoad1_s32
@@ -92,3 +121,37 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            load4_s32_to_sextLoad4_s64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
+    ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
+    ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: $v1 = COPY [[ASHR]](s32)
+    ; MIPS32: RetRA implicit $v0, implicit $v1
+    %0:_(p0) = COPY $a0
+    %5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+    %9:_(s32) = G_CONSTANT i32 31
+    %10:_(s32) = G_CONSTANT i32 0
+    %8:_(s32) = COPY %9(s32)
+    %7:_(s32) = G_ASHR %5, %8(s32)
+    %2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
+    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+    $v0 = COPY %3(s32)
+    $v1 = COPY %4(s32)
+    RetRA implicit $v0, implicit $v1
+
+...
+