bugfix(flash): improve flash dio read timing

When flash work in DIO Mode, in order to ensure the fast read mode of flash
is a fixed value, we merged the mode bits into address part, and the fast
read mode value is 0 (the default value).

diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c
index ca0f435df3120ebd3a1c7f6d6f5f39850b061a71..0353a3b6ac1859b0462f8b1035e48b1cc430f20e 100644 (file)
--- a/components/bootloader_support/src/bootloader_init.c
+++ b/components/bootloader_support/src/bootloader_init.c
@@ -321,10 +321,11 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
     int drv = 2;
     switch (pfhdr->spi_mode) {
         case ESP_IMAGE_SPI_MODE_QIO:
-            spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
+            spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
             break;
         case ESP_IMAGE_SPI_MODE_DIO:
-            spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;   //qio 3
+            spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
+            SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
             break;
         case ESP_IMAGE_SPI_MODE_QOUT:
         case ESP_IMAGE_SPI_MODE_DOUT:

diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c
index f6cda3fa3bb965354d16b962cee846d44e5155e8..fe0299c9bbb1f4d3397fcb8834d48061616430af 100644 (file)
--- a/components/esp32/spiram_psram.c
+++ b/components/esp32/spiram_psram.c
@@ -516,9 +516,11 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t psram_io, psram_cache_mode_t
 {
     int spi_cache_dummy = 0;
     uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));
-    if (rd_mode_reg & (SPI_FREAD_QIO_M | SPI_FREAD_DIO_M)) {
+    if (rd_mode_reg & SPI_FREAD_QIO_M) {
         spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
-    } else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
+    } else if (rd_mode_reg & SPI_FREAD_DIO_M) {
+        spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
+    }  else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
         spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
     } else {
         spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;

diff --git a/components/esp_rom/include/esp32/rom/spi_flash.h b/components/esp_rom/include/esp32/rom/spi_flash.h
index ea25146d7167de6f95f4fbd9a785309b6d2b0f66..ea995e3499aa37982f7ee3e0cc751d3a6ad3b6da 100644 (file)
--- a/components/esp_rom/include/esp32/rom/spi_flash.h
+++ b/components/esp_rom/include/esp32/rom/spi_flash.h
@@ -90,7 +90,8 @@ extern "C" {
 #define SPI0_R_QIO_DUMMY_CYCLELEN             3
 #define SPI0_R_QIO_ADDR_BITSLEN               31
 #define SPI0_R_FAST_DUMMY_CYCLELEN            7
-#define SPI0_R_DIO_DUMMY_CYCLELEN             3
+#define SPI0_R_DIO_DUMMY_CYCLELEN             1
+#define SPI0_R_DIO_ADDR_BITSLEN               27
 #define SPI0_R_FAST_ADDR_BITSLEN              23
 #define SPI0_R_SIO_ADDR_BITSLEN               23
 

diff --git a/components/spi_flash/spi_flash_rom_patch.c b/components/spi_flash/spi_flash_rom_patch.c
index aacc62a7f55e4e67dd532aadb93a3cbfeac76e1a..313a995143161d93e65fbdae5af07716e3b6dc58 100644 (file)
--- a/components/spi_flash/spi_flash_rom_patch.c
+++ b/components/spi_flash/spi_flash_rom_patch.c
@@ -324,6 +324,7 @@ static void spi_cache_mode_switch(uint32_t  modebit)
             REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
             REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
         } else if ((modebit & SPI_FREAD_DIO)) {
+            REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN);
             REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
             REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
         } else if ((modebit & SPI_FREAD_DUAL)) {