Merging r236099:

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r236099 | dsanders | 2015-04-29 13:28:58 +0100 (Wed, 29 Apr 2015) | 13 lines

[mips] Correct 128-bit shifts on 64-bit targets.

Summary:
The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, mohit.bhakkad, sagar

Differential Revision: http://reviews.llvm.org/D9337
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236215 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index bac5c17244519739016647e453dd048955cf1ebf..eb5bb637438c36c80d26fb3c8a2d9c6b653d7a83 100644 (file)
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2069,7 +2069,7 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
   SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
-                             DAG.getConstant(0x20, MVT::i32));
+                             DAG.getConstant(VT.getSizeInBits(), MVT::i32));
   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
                    DAG.getConstant(0, VT), ShiftLeftLo);
   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
@@ -2108,11 +2108,12 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
   SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
                                      DL, VT, Hi, Shamt);
   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
-                             DAG.getConstant(0x20, MVT::i32));
-  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
+                             DAG.getConstant(VT.getSizeInBits(), MVT::i32));
+  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
+                            DAG.getConstant(VT.getSizeInBits() - 1, VT));
   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
-                   IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
+                   IsSRA ? Ext : DAG.getConstant(0, VT), ShiftRightHi);
 
   SDValue Ops[2] = {Lo, Hi};
   return DAG.getMergeValues(Ops, DL);

diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll
index 8866b8bf6f5b590540813f512fef09b4e7f015d3..415998929aa0d2712ba8799d6a7030b81aa85337 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -135,7 +135,7 @@ entry:
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrav     $[[T1:[0-9]+]], $4, $[[T0]]
-  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 32
+  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $[[T0]]
@@ -146,7 +146,7 @@ entry:
   ; M3:             $[[BB0]]:
   ; M3:             beqz      $[[T3]], $[[BB1:BB[0-9_]+]]
   ; M3:             nop
-  ; M3:             dsra      $2, $4, 31
+  ; M3:             dsra      $2, $4, 63
   ; M3:             $[[BB1]]:
   ; M3:             jr        $ra
   ; M3:             nop
@@ -158,19 +158,19 @@ entry:
   ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T1]]
   ; GP64-NOT-R6:    dsrav     $2, $4, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 32
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 64
 
   ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
-  ; GP64-NOT-R6:    dsra      $[[T6:[0-9]+]], $4, 31
+  ; GP64-NOT-R6:    dsra      $[[T6:[0-9]+]], $4, 63
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $2, $[[T6]], $[[T5]]
 
   ; 64R6:           sll       $[[T0:[0-9]+]], $7, 0
   ; 64R6:           dsrav     $[[T1:[0-9]+]], $4, $[[T0]]
-  ; 64R6:           andi      $[[T2:[0-9]+]], $[[T0]], 32
+  ; 64R6:           andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; 64R6:           sll       $[[T3:[0-9]+]], $[[T2]], 0
   ; 64R6:           seleqz    $[[T4:[0-9]+]], $[[T1]], $[[T3]]
-  ; 64R6:           dsra      $[[T5:[0-9]+]], $4, 31
+  ; 64R6:           dsra      $[[T5:[0-9]+]], $4, 63
   ; 64R6:           selnez    $[[T6:[0-9]+]], $[[T5]], $[[T3]]
   ; 64R6:           or        $2, $[[T6]], $[[T4]]
   ; 64R6:           dsrlv     $[[T7:[0-9]+]], $5, $[[T0]]

diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 1679678d5d708f39af7e2db8365b11de2d37d8c8..59f4330dde6c4f74a84a0187710886b967d607b9 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -128,7 +128,7 @@ entry:
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $[[T0]]
-  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 32
+  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $[[T0]]
@@ -151,7 +151,7 @@ entry:
   ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T1]]
   ; GP64-NOT-R6:    dsrlv     $2, $4, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 32
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 64
   ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $2, $zero, $1
@@ -162,7 +162,7 @@ entry:
   ; 64R6:           not       $[[T3:[0-9]+]], $[[T0]]
   ; 64R6:           dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; 64R6:           or        $[[T5:[0-9]+]], $[[T4]], $[[T1]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 32
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 64
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $[[T0]]

diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll
index 072b44aa2a528453f16972fb2866a996f7227d71..fc5243cc97f2e33480c09a37030395a233285e40 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -140,7 +140,7 @@ entry:
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsllv     $[[T1:[0-9]+]], $5, $[[T0]]
-  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 32
+  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $2, $[[T1]]
   ; M3:             dsllv     $[[T4:[0-9]+]], $4, $[[T0]]
@@ -163,7 +163,7 @@ entry:
   ; GP64-NOT-R6:    dsrlv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; GP64-NOT-R6:    or        $2, $[[T1]], $[[T4]]
   ; GP64-NOT-R6:    dsllv     $3, $5, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 32
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 64
   ; GP64-NOT-R6:    movn      $2, $3, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $3, $zero, $1
@@ -174,7 +174,7 @@ entry:
   ; 64R6:           not       $[[T3:[0-9]+]], $[[T0]]
   ; 64R6:           dsrlv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; 64R6:           or        $[[T5:[0-9]+]], $[[T1]], $[[T4]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 32
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 64
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $[[T0]]