[AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions

The STGV/LDGV instructions were replaced with
STGM/LDGM. The encodings remain the same but there
is no longer writeback so there are no unpredictable
encodings to check for.

The specfication can be found here:
https://developer.arm.com/docs/ddi0596/c

Differential Revision: https://reviews.llvm.org/D60064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357395 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index a5428788417f452f39b3764b63f6bbe000591142..abdc530ccccb9088fb8f3a347c62da7202b44e7c 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -4024,7 +4024,7 @@ class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
 class MemTagVector<bit Load, string asm_insn, string asm_opnds,
                    dag oops, dag iops>
     : BaseMemTag<{0b1, Load}, 0b00, asm_insn, asm_opnds,
-                 "$Rn = $wback,@earlyclobber $wback", oops, iops> {
+                  "", oops, iops> {
   bits<5> Rt;
 
   let Inst{20-12} = 0b000000000;

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index fc9987fe0da56bc9d1d870799571ef7c7204238b..347f0104c35be78313e6f60fe90b19f2edc1bc81 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1256,12 +1256,11 @@ def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>;
 def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
 def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
 
-def LDGV : MemTagVector<1, "ldgv", "\t$Rt, [$Rn]!",
-                   (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn)> {
-  let DecoderMethod = "DecodeLoadAllocTagArrayInstruction";
-}
-def STGV : MemTagVector<0, "stgv", "\t$Rt, [$Rn]!",
-                   (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn)>;
+def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
+                   (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
+def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
+                   (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
+
 
 defm STG   : MemTagStore<0b00, "stg">;
 defm STZG  : MemTagStore<0b01, "stzg">;

diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 6d6c3155ba1e94c6285ddd302f64155b32b22b9c..7c3cdb1423e87d2008d69086a439922f282c2381 100644 (file)
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4096,15 +4096,6 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
                    "unpredictable STXP instruction, status is also a source");
     break;
   }
-  case AArch64::LDGV: {
-    unsigned Rt = Inst.getOperand(0).getReg();
-    unsigned Rn = Inst.getOperand(1).getReg();
-    if (RI->isSubRegisterEq(Rt, Rn)) {
-      return Error(Loc[0],
-                  "unpredictable LDGV instruction, writeback register is also "
-                  "the target register");
-    }
-  }
   }
 
 

diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index dc1cf368f8e9cea129ca9081a7962d6cfe679ae9..10f01f4188d8f9488e7ec69314dfaa1865d90c46 100644 (file)
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -219,11 +219,6 @@ static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
                                        uint64_t Addr, const void *Decoder);
 
-static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
-                                                       uint32_t insn,
-                                                       uint64_t address,
-                                                       const void* Decoder);
-
 static bool Check(DecodeStatus &Out, DecodeStatus In) {
   switch (In) {
     case MCDisassembler::Success:
@@ -1851,25 +1846,3 @@ static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
   Inst.addOperand(MCOperand::createImm(Imm + 1));
   return Success;
 }
-
-static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
-                                                       uint32_t insn,
-                                                       uint64_t address,
-                                                       const void* Decoder) {
-  unsigned Rn = fieldFromInstruction(insn, 5, 5);
-  unsigned Rt = fieldFromInstruction(insn, 0, 5);
-
-  // Outputs
-  DecodeGPR64spRegisterClass(Inst, Rn, address, Decoder);
-  DecodeGPR64RegisterClass(Inst, Rt, address, Decoder);
-
-  // Input (Rn again)
-  Inst.addOperand(Inst.getOperand(0));
-
-  //Do this post decode since the raw number for xzr and sp is the same
-  if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
-    return SoftFail;
-  } else {
-    return Success;
-  }
-}

diff --git a/test/MC/AArch64/armv8.5a-mte-error.s b/test/MC/AArch64/armv8.5a-mte-error.s
index 86da34cc35e964a32a5623d44cc692b443943a25..d9af3ba265b9822b6aceb7e78b8dfb23a50b5852 100644 (file)
--- a/test/MC/AArch64/armv8.5a-mte-error.s
+++ b/test/MC/AArch64/armv8.5a-mte-error.s
@@ -813,57 +813,48 @@ ldg x0, [w1]
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: ldg x0, [w1]
 
-ldgv
-ldgv x0
-ldgv x0, [x1]
-ldgv sp, [x0]!
-ldgv x3, [x3]!
-ldgv w0, [x1]!
-ldgv x0, [w1]!
-ldgv #1, [x1]!
-ldgv x0, [#1]!
+ldgm
+ldgm x0
+ldgm w0, [x1]
+ldgm x0, [w1]
+ldgm #1, [x1]
+ldgm x0, [#1]
+ldgm sp, [x0]
 
 // CHECK:      too few operands for instruction
-// CHECK-NEXT: ldgv
+// CHECK-NEXT: ldgm
 // CHECK:      too few operands for instruction
-// CHECK-NEXT: ldgv x0
-// CHECK:      too few operands for instruction
-// CHECK-NEXT: ldgv x0, [x1]
+// CHECK-NEXT: ldgm x0
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: ldgv sp, [x0]!
-// CHECK:      unpredictable LDGV instruction, writeback register is also the target register
-// CHECK-NEXT: ldgv x3, [x3]!
+// CHECK-NEXT: ldgm w0, [x1]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: ldgv w0, [x1]!
+// CHECK-NEXT: ldgm x0, [w1]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: ldgv x0, [w1]!
+// CHECK-NEXT: ldgm #1, [x1]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: ldgv #1, [x1]!
+// CHECK-NEXT: ldgm x0, [#1]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: ldgv x0, [#1]!
+// CHECK-NEXT: ldgm sp, [x0]
 
-stgv
-stgv x0
-stgv x0, [x1]
-stgv sp, [x0]!
-stgv w0, [x0]!
-stgv x0, [w0]!
-stgv #1, [x1]!
-stgv x0, [#1]!
+stgm
+stgm x0
+stgm sp, [x0]
+stgm w0, [x0]
+stgm x0, [w0]
+stgm #1, [x1]
+stgm x0, [#1]
 
 // CHECK:      too few operands for instruction
-// CHECK-NEXT: stgv
-// CHECK:      too few operands for instruction
-// CHECK-NEXT: stgv x0
+// CHECK-NEXT: stgm
 // CHECK:      too few operands for instruction
-// CHECK-NEXT: stgv x0, [x1]
+// CHECK-NEXT: stgm x0
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: stgv sp, [x0]!
+// CHECK-NEXT: stgm sp, [x0]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: stgv w0, [x0]!
+// CHECK-NEXT: stgm w0, [x0]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: stgv x0, [w0]!
+// CHECK-NEXT: stgm x0, [w0]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: stgv #1, [x1]!
+// CHECK-NEXT: stgm #1, [x1]
 // CHECK:      invalid operand for instruction
-// CHECK-NEXT: stgv x0, [#1]!
+// CHECK-NEXT: stgm x0, [#1]

diff --git a/test/MC/AArch64/armv8.5a-mte.s b/test/MC/AArch64/armv8.5a-mte.s
index 59da9c5ddb4371e2ad3cd9a1e80056655005bc56..bd0d99e37a93e264366a7413f315c88ff6ba3102 100644 (file)
--- a/test/MC/AArch64/armv8.5a-mte.s
+++ b/test/MC/AArch64/armv8.5a-mte.s
@@ -534,24 +534,24 @@ ldg x3, [x4, #4080]
 // NOMTE: instruction requires: mte
 // NOMTE: instruction requires: mte
 
-ldgv x0, [x1]!
-ldgv x1, [sp]!
-ldgv xzr, [x2]!
+ldgm x0, [x1]
+ldgm x1, [sp]
+ldgm xzr, [x2]
 
-// CHECK: ldgv x0, [x1]!  // encoding: [0x20,0x00,0xe0,0xd9]
-// CHECK: ldgv x1, [sp]!  // encoding: [0xe1,0x03,0xe0,0xd9]
-// CHECK: ldgv xzr, [x2]! // encoding: [0x5f,0x00,0xe0,0xd9]
+// CHECK: ldgm x0, [x1]  // encoding: [0x20,0x00,0xe0,0xd9]
+// CHECK: ldgm x1, [sp]  // encoding: [0xe1,0x03,0xe0,0xd9]
+// CHECK: ldgm xzr, [x2] // encoding: [0x5f,0x00,0xe0,0xd9]
 
 // NOMTE: instruction requires: mte
 // NOMTE: instruction requires: mte
 
-stgv x0, [x1]!
-stgv x1, [sp]!
-stgv xzr, [x2]!
+stgm x0, [x1]
+stgm x1, [sp]
+stgm xzr, [x2]
 
-// CHECK: stgv x0, [x1]!  // encoding: [0x20,0x00,0xa0,0xd9]
-// CHECK: stgv x1, [sp]!  // encoding: [0xe1,0x03,0xa0,0xd9]
-// CHECK: stgv xzr, [x2]! // encoding: [0x5f,0x00,0xa0,0xd9]
+// CHECK: stgm x0, [x1]  // encoding: [0x20,0x00,0xa0,0xd9]
+// CHECK: stgm x1, [sp]  // encoding: [0xe1,0x03,0xa0,0xd9]
+// CHECK: stgm xzr, [x2] // encoding: [0x5f,0x00,0xa0,0xd9]
 
 // NOMTE: instruction requires: mte
 // NOMTE: instruction requires: mte

diff --git a/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt b/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt
deleted file mode 100644 (file)
index b108d12..0000000
--- a/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# RUN:     llvm-mc -triple=aarch64 -mattr=+mte   -disassemble < %s 2>&1 | FileCheck %s
-
-# ldgv x1, [x1]!
-[0x21,0x00,0xe0,0xd9]
-
-# CHECK:      warning: potentially undefined instruction encoding
-# CHECK-NEXT: [0x21,0x00,0xe0,0xd9]

diff --git a/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
index b714bb4ea13f039a73f6e522d5f587109c8000ef..4cded66f40c1e1febb0073f0537af9f062eea6e8 100644 (file)
--- a/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
+++ b/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
@@ -408,12 +408,12 @@
 [0xe1,0x03,0xa0,0xd9]
 [0x5f,0x00,0xa0,0xd9]
 
-# CHECK: ldgv x0, [x1]!
-# CHECK: ldgv x1, [sp]!
-# CHECK: ldgv xzr, [x2]!
-# CHECK: stgv x0, [x1]!
-# CHECK: stgv x1, [sp]!
-# CHECK: stgv xzr, [x2]!
+# CHECK: ldgm x0, [x1]
+# CHECK: ldgm x1, [sp]
+# CHECK: ldgm xzr, [x2]
+# CHECK: stgm x0, [x1]
+# CHECK: stgm x1, [sp]
+# CHECK: stgm xzr, [x2]
 
 # NOMTE:      warning: invalid instruction encoding
 # NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]