Revert Fix and test inter-procedural register allocation for ARM

This reverts r367669 (git commit f6b00c279a5587a25876752a6ecd8da0bed959dc)

This was breaking a build bot http://lab.llvm.org:8011/builders/netbsd-amd64/builds/21233

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367731 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/TargetRegisterInfo.h b/include/llvm/CodeGen/TargetRegisterInfo.h
index 11596cb7ee7c45514c0aa3db3d6a35a1275743be..7fac869b70100875c0f20e4a616196fd201a9f26 100644 (file)
--- a/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -447,14 +447,6 @@ public:
     llvm_unreachable("target does not provide no preserved mask");
   }
 
-  /// Return a list of all of the registers which are clobbered "inside" a call
-  /// to the given function. For example, these might be needed for PLT
-  /// sequences of long-branch veneers.
-  virtual ArrayRef<MCPhysReg>
-  getIntraCallClobberedRegs(const MachineFunction *MF) const {
-    return {};
-  }
-
   /// Return true if all bits that are set in mask \p mask0 are also set in
   /// \p mask1.
   bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;

diff --git a/lib/CodeGen/RegUsageInfoCollector.cpp b/lib/CodeGen/RegUsageInfoCollector.cpp
index 757ff0e44953dcaf0366c8a65e57c6c2385aab09..c12e51bd3bf8ca3ceb5b63b7d6f608b444a4a71e 100644 (file)
--- a/lib/CodeGen/RegUsageInfoCollector.cpp
+++ b/lib/CodeGen/RegUsageInfoCollector.cpp
@@ -142,13 +142,6 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
   auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
     RegMask[Reg / 32] &= ~(1u << Reg % 32);
   };
-
-  // Some targets can clobber registers "inside" a call, typically in
-  // linker-generated code.
-  for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
-    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
-      SetRegAsDefined(*AI);
-
   // Scan all the physical registers. When a register is defined in the current
   // function set it and all the aliasing registers as defined in the regmask.
   // FIXME: Rewrite to use regunits.

diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index b131227d49e7b727d46b5c0c841a552114da7d7a..e63ea7a444763a2a896587f957a34d66cc853e99 100644 (file)
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -174,12 +174,6 @@ ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
                               : CSR_AAPCS_ThisReturn_RegMask;
 }
 
-ArrayRef<MCPhysReg> ARMBaseRegisterInfo::getIntraCallClobberedRegs(
-    const MachineFunction *MF) const {
-  static MCPhysReg IntraCallClobberedRegs[] = {ARM::R12};
-  return IntraCallClobberedRegs;
-}
-
 BitVector ARMBaseRegisterInfo::
 getReservedRegs(const MachineFunction &MF) const {
   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();

diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h
index 37248ac6ecf8cc46faa9a919cb120c4348f84b3f..7e2c72b4d712c1bd19c737d39a12ee7248b8c345 100644 (file)
--- a/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -129,9 +129,6 @@ public:
   const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
                                              CallingConv::ID) const;
 
-  ArrayRef<MCPhysReg>
-  getIntraCallClobberedRegs(const MachineFunction *MF) const override;
-
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                        unsigned PhysReg) const override;

diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp
index d2a5111a4def3337c15408c53ae81c0382c46a0e..7ae0c6ab3cf8ed38856c2466c55052b2a68a5446 100644 (file)
--- a/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/lib/Target/ARM/ARMFrameLowering.cpp
@@ -2080,8 +2080,9 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
             ExtraCSSpill = true;
         }
       }
-      if (!ExtraCSSpill && RS) {
+      if (!ExtraCSSpill) {
         // Reserve a slot closest to SP or frame pointer.
+        assert(RS && "Register scavenging not provided");
         LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n");
         const TargetRegisterClass &RC = ARM::GPRRegClass;
         unsigned Size = TRI->getSpillSize(RC);

diff --git a/test/CodeGen/ARM/ipra.ll b/test/CodeGen/ARM/ipra.ll
deleted file mode 100644 (file)
index 3252c13..0000000
--- a/test/CodeGen/ARM/ipra.ll
+++ /dev/null
@@ -1,202 +0,0 @@
-; RUN: llc -mtriple armv7a--none-eabi < %s              | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
-; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLED
-
-define void @leaf()  {
-entry:
-  tail call void asm sideeffect "", ""()
-  ret void
-}
-
-define void @leaf_r3() {
-entry:
-  tail call void asm sideeffect "", "~{r3}"()
-  ret void
-}
-
-define void @leaf_r4() {
-entry:
-  tail call void asm sideeffect "", "~{r4}"()
-  ret void
-}
-
-define void @leaf_s0() {
-entry:
-  tail call void asm sideeffect "", "~{s0}"()
-  ret void
-}
-
-define void @leaf_d0() {
-entry:
-  tail call void asm sideeffect "", "~{d0}"()
-  ret void
-}
-
-; r3 is normally caller-saved, but with IPRA we can see that it isn't used in
-; the callee, so can leave a live value in it.
-define void @test_r3_presrved() {
-; CHECK-LABEL: test_r3_presrved:
-entry:
-; CHECK: ASM1: r3
-; DISABLED: mov [[TEMP:r[0-9]+]], r3
-; ENABLED-NOT: r3
-; CHECK: bl      leaf
-; DISABLED: mov r3, [[TEMP]]
-; ENABLED-NOT: r3
-; CHECK: ASM2: r3
-  %a = tail call i32 asm sideeffect "// ASM1: $0", "={r3},0"(i32 undef)
-  tail call void @leaf()
-  %b = tail call i32 asm sideeffect "// ASM2: $0", "={r3},0"(i32 %a)
-  ret void
-}
-
-; Same as above, but r3 is clobbered in the callee, so it is clobbered by the
-; call as normal.
-define void @test_r3_clobbered() {
-; CHECK-LABEL: test_r3_clobbered:
-entry:
-; CHECK: ASM1: r3
-; CHECK: mov [[TEMP:r[0-9]+]], r3
-; CHECK: bl      leaf
-; CHECK: mov r3, [[TEMP]]
-; CHECK: ASM2: r3
-  %a = tail call i32 asm sideeffect "// ASM1: $0", "={r3},0"(i32 undef)
-  tail call void @leaf_r3()
-  %b = tail call i32 asm sideeffect "// ASM2: $0", "={r3},0"(i32 %a)
-  ret void
-}
-
-; r4 is a callee-saved register, so IPRA has no effect.
-define void @test_r4_preserved() {
-; CHECK-LABEL: test_r4_preserved:
-entry:
-; CHECK: ASM1: r4
-; CHECK-NOT: r4
-; CHECK: bl      leaf
-; CHECK-NOT: r4
-; CHECK: ASM2: r4
-  %a = tail call i32 asm sideeffect "// ASM1: $0", "={r4},0"(i32 undef)
-  tail call void @leaf()
-  %b = tail call i32 asm sideeffect "// ASM2: $0", "={r4},0"(i32 %a)
-  ret void
-}
-define void @test_r4_clobbered() {
-; CHECK-LABEL: test_r4_clobbered:
-entry:
-; CHECK: ASM1: r4
-; CHECK-NOT: r4
-; CHECK: bl      leaf_r4
-; CHECK-NOT: r4
-; CHECK: ASM2: r4
-  %a = tail call i32 asm sideeffect "// ASM1: $0", "={r4},0"(i32 undef)
-  tail call void @leaf_r4()
-  %b = tail call i32 asm sideeffect "// ASM2: $0", "={r4},0"(i32 %a)
-  ret void
-}
-
-; r12 is the intra-call scratch register, so we have to assume it is clobbered
-; even if we can see that the callee does not touch it.
-define void @test_r12() {
-; CHECK-LABEL: test_r12:
-entry:
-; CHECK: ASM1: r12
-; CHECK: mov [[TEMP:r[0-9]+]], r12
-; CHECK: bl      leaf
-; CHECK: mov r12, [[TEMP]]
-; CHECK: ASM2: r12
-  %a = tail call i32 asm sideeffect "// ASM1: $0", "={r12},0"(i32 undef)
-  tail call void @leaf()
-  %b = tail call i32 asm sideeffect "// ASM2: $0", "={r12},0"(i32 %a)
-  ret void
-}
-
-; s0 and d0 are caller-saved, IPRA allows us to keep them live in the caller if
-; the callee doesn't modify them.
-define void @test_s0_preserved() {
-; CHECK-LABEL: test_s0_preserved:
-entry:
-; CHECK: ASM1: s0
-; DISABLED: vmov.f32 [[TEMP:s[0-9]+]], s0
-; ENABLED-NOT: s0
-; CHECK: bl      leaf
-; DISABLED: vmov.f32 s0, [[TEMP]]
-; ENABLED-NOT: s0
-; CHECK: ASM2: s0
-  %a = tail call float asm sideeffect "// ASM1: $0", "={s0},0"(float undef)
-  tail call void @leaf()
-  %b = tail call float asm sideeffect "// ASM2: $0", "={s0},0"(float %a)
-  ret void
-}
-
-define void @test_s0_clobbered() {
-; CHECK-LABEL: test_s0_clobbered:
-entry:
-; CHECK: ASM1: s0
-; CHECK: vmov.f32 [[TEMP:s[0-9]+]], s0
-; CHECK: bl      leaf_s0
-; CHECK: vmov.f32 s0, [[TEMP]]
-; CHECK: ASM2: s0
-  %a = tail call float asm sideeffect "// ASM1: $0", "={s0},0"(float undef)
-  tail call void @leaf_s0()
-  %b = tail call float asm sideeffect "// ASM2: $0", "={s0},0"(float %a)
-  ret void
-}
-
-define void @test_d0_preserved() {
-; CHECK-LABEL: test_d0_preserved:
-entry:
-; CHECK: ASM1: d0
-; DISABLED: vmov.f64 [[TEMP:d[0-9]+]], d0
-; ENABLED-NOT: d0
-; CHECK: bl      leaf
-; DISABLED: vmov.f64 d0, [[TEMP]]
-; ENABLED-NOT: d0
-; CHECK: ASM2: d0
-  %a = tail call double asm sideeffect "// ASM1: $0", "={d0},0"(double undef)
-  tail call void @leaf()
-  %b = tail call double asm sideeffect "// ASM2: $0", "={d0},0"(double %a)
-  ret void
-}
-
-define void @test_d0_clobbered() {
-; CHECK-LABEL: test_d0_clobbered:
-entry:
-; CHECK: ASM1: d0
-; CHECK: vmov.f64 [[TEMP:d[0-9]+]], d0
-; CHECK: bl      leaf_d0
-; CHECK: vmov.f64 d0, [[TEMP]]
-; CHECK: ASM2: d0
-  %a = tail call double asm sideeffect "// ASM1: $0", "={d0},0"(double undef)
-  tail call void @leaf_d0()
-  %b = tail call double asm sideeffect "// ASM2: $0", "={d0},0"(double %a)
-  ret void
-}
-
-; s0 and d0 overlap, so clobbering one in the callee prevents the other from
-; being kept live across the call.
-define void @test_s0_clobber_d0() {
-; CHECK-LABEL: test_s0_clobber_d0:
-entry:
-; CHECK: ASM1: s0
-; CHECK: vmov.f32 [[TEMP:s[0-9]+]], s0
-; CHECK: bl      leaf_d0
-; CHECK: vmov.f32 s0, [[TEMP]]
-; CHECK: ASM2: s0
-  %a = tail call float asm sideeffect "// ASM1: $0", "={s0},0"(float undef)
-  tail call void @leaf_d0()
-  %b = tail call float asm sideeffect "// ASM2: $0", "={s0},0"(float %a)
-  ret void
-}
-
-define void @test_d0_clobber_s0() {
-; CHECK-LABEL: test_d0_clobber_s0:
-entry:
-; CHECK: ASM1: d0
-; CHECK: vmov.f64 [[TEMP:d[0-9]+]], d0
-; CHECK: bl      leaf_s0
-; CHECK: vmov.f64 d0, [[TEMP]]
-; CHECK: ASM2: d0
-  %a = tail call double asm sideeffect "// ASM1: $0", "={d0},0"(double undef)
-  tail call void @leaf_s0()
-  %b = tail call double asm sideeffect "// ASM2: $0", "={d0},0"(double %a)
-  ret void
-}