]> granicus.if.org Git - llvm/commitdiff
SDag: fix how initial loads are formed when splitting vector ops.
authorTim Northover <tnorthover@apple.com>
Wed, 25 Jan 2017 20:58:26 +0000 (20:58 +0000)
committerTim Northover <tnorthover@apple.com>
Wed, 25 Jan 2017 20:58:26 +0000 (20:58 +0000)
Later code expects the vector loads produced to be directly
concatenable, which means we shouldn't pad anything except the last load
produced with UNDEF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293088 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
test/CodeGen/ARM/vector-load.ll

index df7846cb57430578a2e41f1424c229fe1382d064..74740d1641adeb96e477c2d3e6aa4fd6b8f3c3cc 100644 (file)
@@ -3442,7 +3442,10 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
                       LD->getPointerInfo().getWithOffset(Offset),
                       MinAlign(Align, Increment), MMOFlags, AAInfo);
       LdChain.push_back(L.getValue(1));
-      if (L->getValueType(0).isVector()) {
+      if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
+        // Later code assumes the vector loads produced will be mergeable, so we
+        // must pad the final entry up to the previous width. Scalars are
+        // combined separately.
         SmallVector<SDValue, 16> Loads;
         Loads.push_back(L);
         unsigned size = L->getValueSizeInBits(0);
index a638c2bdb9beddec6ebe3741b7347c591bca6135..ed734723a86d34012e04308fed5e35e26c700548 100644 (file)
@@ -251,3 +251,13 @@ define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
         %zlA = zext <4 x i8> %lA to <4 x i32>
        ret <4 x i32> %zlA
 }
+
+; CHECK-LABEL: test_silly_load:
+; CHECK: ldr {{r[0-9]+}}, [r0, #24]
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:128]!
+; CHECK: vldr d{{[0-9]+}}, [r0]
+
+define void @test_silly_load(<28 x i8>* %addr) {
+  load volatile <28 x i8>, <28 x i8>* %addr
+  ret void
+}