SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
"txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
- SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL || esp_ptr_dma_capable(trans_desc->rx_buffer),
- "rxdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
+ SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL ||
+ (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) &&
+ (trans_desc->length%4==0)),
+ "rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG);
r = xQueueSend(spihost[host]->trans_queue, (void *)&trans_desc, ticks_to_wait);
TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, 2) );
}
-TEST_CASE("test slave startup","[spi]")
+TEST_CASE("test slave send unaligned","[spi]")
{
- uint8_t master_txbuf[320]=MASTER_SEND;
- uint8_t master_rxbuf[320];
- uint8_t slave_txbuf[320]=SLAVE_SEND;
- uint8_t slave_rxbuf[320];
+ WORD_ALIGNED_ATTR uint8_t master_txbuf[320]=MASTER_SEND;
+ WORD_ALIGNED_ATTR uint8_t master_rxbuf[320];
+ WORD_ALIGNED_ATTR uint8_t slave_txbuf[320]=SLAVE_SEND;
+ WORD_ALIGNED_ATTR uint8_t slave_rxbuf[320];
spi_device_handle_t spi;
//initial master
int_connect( PIN_NUM_CS, HSPICS0_OUT_IDX, VSPICS0_IN_IDX );
int_connect( PIN_NUM_CLK, HSPICLK_OUT_IDX, VSPICLK_IN_IDX );
- for ( int i = 0; i < 3; i ++ ) {
+ for ( int i = 0; i < 4; i ++ ) {
//slave send
spi_slave_transaction_t slave_t;
spi_slave_transaction_t* out;
memset(&slave_t, 0, sizeof(spi_slave_transaction_t));
slave_t.length=8*32;
- slave_t.tx_buffer=slave_txbuf+2*i;
+ slave_t.tx_buffer=slave_txbuf+i;
slave_t.rx_buffer=slave_rxbuf;
TEST_ESP_OK( spi_slave_queue_trans( VSPI_HOST, &slave_t, portMAX_DELAY ) );
The ESP32 has four SPI peripheral devices, called SPI0, SPI1, HSPI and VSPI. SPI0 is entirely dedicated to
the flash cache the ESP32 uses to map the SPI flash device it is connected to into memory. SPI1 is
connected to the same hardware lines as SPI0 and is used to write to the flash chip. HSPI and VSPI
-are free to use, and with the spi_slave driver, these can be used as a SPI slave, driven from a
+are free to use, and with the spi_slave driver, these can be used as a SPI slave, driven from a
connected SPI master.
The spi_slave driver
The spi_slave driver uses the following terms:
-* Host: The SPI peripheral inside the ESP32 initiating the SPI transmissions. One of HSPI or VSPI.
+* Host: The SPI peripheral inside the ESP32 initiating the SPI transmissions. One of HSPI or VSPI.
* Bus: The SPI bus, common to all SPI devices connected to a master. In general the bus consists of the
- miso, mosi, sclk and optionally quadwp and quadhd signals. The SPI slaves are connected to these
+ miso, mosi, sclk and optionally quadwp and quadhd signals. The SPI slaves are connected to these
signals in parallel. Each SPI slave is also connected to one CS signal.
- miso - Also known as q, this is the output of the serial stream from the ESP32 to the SPI master
Using the spi_slave driver
^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Initialize a SPI peripheral as a slave by calling ``spi_slave_initialize``. Make sure to set the
+- Initialize a SPI peripheral as a slave by calling ``spi_slave_initialize``. Make sure to set the
correct IO pins in the ``bus_config`` struct. Take care to set signals that are not needed to -1.
A DMA channel (either 1 or 2) must be given if transactions will be larger than 32 bytes, if not
the dma_chan parameter may be 0.
-- To set up a transaction, fill one or more spi_transaction_t structure with any transaction
+- To set up a transaction, fill one or more spi_transaction_t structure with any transaction
parameters you need. Either queue all transactions by calling ``spi_slave_queue_trans``, later
quering the result using ``spi_slave_get_trans_result``, or handle all requests synchroneously
- by feeding them into ``spi_slave_transmit``. The latter two functions will block until the
+ by feeding them into ``spi_slave_transmit``. The latter two functions will block until the
master has initiated and finished a transaction, causing the queued data to be sent and received.
- Optional: to unload the SPI slave driver, call ``spi_slave_free``.
Normally, data to be transferred to or from a device will be read from or written to a chunk of memory
indicated by the ``rx_buffer`` and ``tx_buffer`` members of the transaction structure. The SPI driver
-may decide to use DMA for transfers, so these buffers should be allocated in DMA-capable memory using
+may decide to use DMA for transfers, so these buffers should be allocated in DMA-capable memory using
``pvPortMallocCaps(size, MALLOC_CAP_DMA)``.
The amount of data written to the buffers is limited by the ``length`` member of the transaction structure:
transferred can be read from the ``trans_len`` member of the ``spi_slave_transaction_t`` structure after transaction.
In case the length of the transmission is larger than the buffer length, only the start of the transmission
will be sent and received, and the ``trans_len`` is set to ``length`` instead of the actual length. It's recommended to
-set ``length`` longer than the maximum length expected if the ``trans_len`` is required. In case the transmission
+set ``length`` longer than the maximum length expected if the ``trans_len`` is required. In case the transmission
length is shorter than the buffer length, only data up to the length of the buffer will be exchanged.
-Warning: Due to a design peculiarity in the ESP32, if the amount of bytes sent by the master or the length
-of the transmission queues in the slave driver, in bytes, is not both larger than eight and dividable by
+Warning: Due to a design peculiarity in the ESP32, if the amount of bytes sent by the master or the length
+of the transmission queues in the slave driver, in bytes, is not both larger than eight and dividable by
four, the SPI hardware can fail to write the last one to seven bytes to the receive buffer.
+Restrictions and Known issues
+-------------------------------
+
+1. If the DMA is enabled, the rx buffer should be WORD aligned, i.e. Start
+ from the boundary of 32-bit and have length of multiples of 4 bytes. Or the
+ DMA may write incorrectly or out of the boundary.The driver will check for
+ this.
+
+ Also, master should write lengths which are a multiple of 4 bytes. Data
+ longer than that will be discarded.
Application Example
-------------------
projects / esp-idf / commitdiff