[Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTEND

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354473 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index d34d189ceaf555a3a3a02701436f4b8b52a6ee11..605fcfc25559de50889427be6ffb8d7d970b874d 100644 (file)
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -848,6 +848,9 @@ void HexagonDAGToDAGISel::SelectD2P(SDNode *N) {
 void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
   const SDLoc &dl(N);
   MVT ResTy = N->getValueType(0).getSimpleVT();
+  // The argument to V2Q should be a single vector.
+  MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
+  assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
 
   SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
   SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
@@ -859,6 +862,8 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
 void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
   const SDLoc &dl(N);
   MVT ResTy = N->getValueType(0).getSimpleVT();
+  // The result of V2Q should be a single vector.
+  assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
 
   SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
   SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);

diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 6ab35c39bd477f50e64f47686d3179bc784ec35c..345c657787a05806bce6abb7123a4f5b3324f618 100644 (file)
--- a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1541,6 +1541,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
       case ISD::SRL:
       case ISD::SETCC:
       case ISD::VSELECT:
+      case ISD::SIGN_EXTEND:
+      case ISD::ZERO_EXTEND:
       case ISD::SIGN_EXTEND_INREG:
         return SplitHvxPairOp(Op, DAG);
     }

diff --git a/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll b/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
new file mode 100644 (file)
index 0000000..e2fa59b
--- /dev/null
+++ b/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
@@ -0,0 +1,16 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure that this doesn't crash.
+; CHECK: vadd
+
+define void @foo(<64 x i32>* %a0, <64 x i32>* %a1) #0 {
+  %v0 = load <64 x i32>, <64 x i32>* %a0, align 128
+  %v1 = load <64 x i32>, <64 x i32>* %a1, align 128
+  %v2 = icmp sgt <64 x i32> %v0, zeroinitializer
+  %v3 = sext <64 x i1> %v2 to <64 x i32>
+  %v4 = add nsw <64 x i32> %v1, %v3
+  store <64 x i32> %v4, <64 x i32>* %a1, align 128
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b" }