[MIRParser] Allow generic register specification on operand.

This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MIRParser/MIParser.cpp b/lib/CodeGen/MIRParser/MIParser.cpp
index ff6d30979592fbc3bc2ec3ed7cc51f58b75b4141..e302de26d1fb7897c29e09df76cbdab4a81d594c 100644 (file)
--- a/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/lib/CodeGen/MIRParser/MIParser.cpp
@@ -883,8 +883,8 @@ bool MIParser::parseRegister(unsigned &Reg, VRegInfo *&Info) {
 }
 
 bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
-  if (Token.isNot(MIToken::Identifier))
-    return error("expected a register class or register bank name");
+  if (Token.isNot(MIToken::Identifier) && Token.isNot(MIToken::underscore))
+    return error("expected '_', register class, or register bank name");
   StringRef::iterator Loc = Token.location();
   StringRef Name = Token.stringValue();
 
@@ -914,26 +914,30 @@ bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
     llvm_unreachable("Unexpected register kind");
   }
 
-  // Should be a register bank.
-  auto RBNameI = PFS.Names2RegBanks.find(Name);
+  // Should be a register bank or a generic register.
+  const RegisterBank *RegBank = nullptr;
+  if (Name != "_") {
+    auto RBNameI = PFS.Names2RegBanks.find(Name);
+    if (RBNameI == PFS.Names2RegBanks.end())
+      return error(Loc, "expected '_', register class, or register bank name");
+    RegBank = RBNameI->getValue();
+  }
+
   lex();
-  if (RBNameI == PFS.Names2RegBanks.end())
-    return error(Loc, "expected a register class or register bank name");
 
-  const RegisterBank &RegBank = *RBNameI->getValue();
   switch (RegInfo.Kind) {
   case VRegInfo::UNKNOWN:
   case VRegInfo::GENERIC:
   case VRegInfo::REGBANK:
-    RegInfo.Kind = VRegInfo::REGBANK;
-    if (RegInfo.Explicit && RegInfo.D.RegBank != &RegBank)
-      return error(Loc, "conflicting register banks");
-    RegInfo.D.RegBank = &RegBank;
+    RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC;
+    if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank)
+      return error(Loc, "conflicting generic register banks");
+    RegInfo.D.RegBank = RegBank;
     RegInfo.Explicit = true;
     return false;
 
   case VRegInfo::NORMAL:
-    return error(Loc, "register class specification on normal register");
+    return error(Loc, "register bank specification on normal register");
   }
   llvm_unreachable("Unexpected register kind");
 }

diff --git a/test/CodeGen/MIR/X86/register-operand-class.mir b/test/CodeGen/MIR/X86/register-operand-class.mir
index d21622b68a41bec853bbad63d417dd53bad963b7..63019daad7a18c3230429d4ac9d0eceb203a327c 100644 (file)
--- a/test/CodeGen/MIR/X86/register-operand-class.mir
+++ b/test/CodeGen/MIR/X86/register-operand-class.mir
@@ -10,6 +10,7 @@
 # CHECK:   - { id: 1, class: gr64 }
 # CHECK:   - { id: 2, class: gr32 }
 # CHECK:   - { id: 3, class: gr16 }
+# CHECK:   - { id: 4, class: _ }
 name: func
 body: |
   bb.0:
@@ -21,4 +22,6 @@ body: |
 
     %3 : gr16 = COPY %bx
     %bx = COPY %3 : gr16
+
+    %4 : _(s32) = COPY %edx
 ...