vbsl, vrev* is implemented via arm_neon.h

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@105875 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/clang/Basic/BuiltinsARM.def b/include/clang/Basic/BuiltinsARM.def
index 247cf7f5abfeee0d190884f4a2f6f86ddb29f8d2..3172e65fef59266d059787e071c04d315ed491d5 100644 (file)
--- a/include/clang/Basic/BuiltinsARM.def
+++ b/include/clang/Basic/BuiltinsARM.def
@@ -30,8 +30,6 @@ BUILTIN(__builtin_neon_vabsq_v, "V16cV16ci", "n")
 BUILTIN(__builtin_neon_vaddhn_v, "V8cV16cV16ci", "n")
 BUILTIN(__builtin_neon_vaddl_v, "V16cV8cV8ci", "n")
 BUILTIN(__builtin_neon_vaddw_v, "V16cV16cV8ci", "n")
-BUILTIN(__builtin_neon_vbsl_v, "V8cV8cV8cV8ci", "n")
-BUILTIN(__builtin_neon_vbslq_v, "V16cV16cV16cV16ci", "n")
 BUILTIN(__builtin_neon_vcage_v, "V8cV8cV8ci", "n")
 BUILTIN(__builtin_neon_vcageq_v, "V16cV16cV16ci", "n")
 BUILTIN(__builtin_neon_vcagt_v, "V8cV8cV8ci", "n")
@@ -161,12 +159,6 @@ BUILTIN(__builtin_neon_vrecpe_v, "V8cV8ci", "n")
 BUILTIN(__builtin_neon_vrecpeq_v, "V16cV16ci", "n")
 BUILTIN(__builtin_neon_vrecps_v, "V8cV8cV8ci", "n")
 BUILTIN(__builtin_neon_vrecpsq_v, "V16cV16cV16ci", "n")
-BUILTIN(__builtin_neon_vrev16_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vrev16q_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vrev32_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vrev32q_v, "V16cV16ci", "n")
-BUILTIN(__builtin_neon_vrev64_v, "V8cV8ci", "n")
-BUILTIN(__builtin_neon_vrev64q_v, "V16cV16ci", "n")
 BUILTIN(__builtin_neon_vrhadd_v, "V8cV8cV8ci", "n")
 BUILTIN(__builtin_neon_vrhaddq_v, "V16cV16cV16ci", "n")
 BUILTIN(__builtin_neon_vrshl_v, "V8cV8cV8ci", "n")

diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp
index 703d353ac2f3e419bc885ff679db6ccb021395e9..c857e27d972f51a2640c8a94d798fd720e95fe3b 100644 (file)
--- a/lib/CodeGen/CGBuiltin.cpp
+++ b/lib/CodeGen/CGBuiltin.cpp
@@ -991,7 +991,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
   case ARM::BI__builtin_neon_vaddw_v:
     Int = usgn ? Intrinsic::arm_neon_vaddws : Intrinsic::arm_neon_vaddwu;
     return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vaddw");
-  // FIXME: vbsl -> or ((0 & 1), (0 & 2)) in arm_neon.h
   case ARM::BI__builtin_neon_vcale_v:
     std::swap(Ops[0], Ops[1]);
   case ARM::BI__builtin_neon_vcage_v: {
@@ -1218,7 +1217,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
   case ARM::BI__builtin_neon_vrecpsq_v:
     return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecps, &Ty, 1),
                         Ops, "vrecps");
-  // FIXME: rev16, 32, 16 -> shufflevector
   case ARM::BI__builtin_neon_vrhadd_v:
   case ARM::BI__builtin_neon_vrhaddq_v:
     Int = usgn ? Intrinsic::arm_neon_vrhaddu : Intrinsic::arm_neon_vrhadds;

diff --git a/lib/Headers/arm_neon.td b/lib/Headers/arm_neon.td
index fb298a67c69925ed60fc0c0f5c5380afdb49ae3a..c833dc03100b96002b8c825e29b69fa974100dbd 100644 (file)
--- a/lib/Headers/arm_neon.td
+++ b/lib/Headers/arm_neon.td
@@ -40,6 +40,10 @@ def OP_HI    : Op;
 def OP_LO    : Op;
 def OP_CONC  : Op;
 def OP_DUP   : Op;
+def OP_SEL   : Op;
+def OP_REV64 : Op;
+def OP_REV32 : Op;
+def OP_REV16 : Op;
 
 class Inst <string p, string t, Op o> {
   string Prototype = p;
@@ -298,9 +302,9 @@ def VEXT : WInst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // E.3.27 Reverse vector elements (sdap endianness)
-def VREV64 : WInst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf">;
-def VREV32 : WInst<"dd", "csUcUsPcQcQsQUcQUsQPc">;
-def VREV16 : WInst<"dd", "cUcPcQcQUcQPc">;
+def VREV64 : Inst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", OP_REV64>;
+def VREV32 : Inst<"dd", "csUcUsPcQcQsQUcQUsQPc", OP_REV32>;
+def VREV16 : Inst<"dd", "cUcPcQcQUcQPc", OP_REV16>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // E.3.28 Other single operand arithmetic
@@ -322,7 +326,7 @@ def VORR : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
 def VEOR : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
 def VBIC : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
 def VORN : Inst<"ddd",   "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
-def VBSL : SInst<"dudd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
+def VBSL : Inst<"dudd",  "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // E.3.30 Transposition operations