[AArch64][SVE] Asm: Support for predicated FP operations.

This patch adds support for the following floating point
instructions:
  FABD   (absolute difference)
  FADD   (addition)
  FSUB   (subtract)
  FSUBR  (subtract reverse form)
  FDIV   (divide)
  FDIVR  (divide reverse form)
  FMAX   (maximum)
  FMAXNM (maximum number)
  FMIN   (minimum)
  FMINNM (minimum number)
  FSCALE (adjust exponent)
  FMULX  (multiply extended)

All operations are predicated and binary form, e.g.

  fadd z0.h, p0/m, z0.h, z1.h
        ^___________^ (tied)

Supporting 16, 32 and 64-bit FP elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337259 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 1edc36944a14eaf97389572748182070549b0467..521253baf635b65a45b3ac01b2de5b5f701f3d51 100644 (file)
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -85,6 +85,20 @@ let Predicates = [HasSVE] in {
   defm FMUL_ZPmI    : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
   defm FMAX_ZPmI    : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
 
+  defm FADD_ZPmZ   : sve_fp_2op_p_zds<0b0000, "fadd">;
+  defm FSUB_ZPmZ   : sve_fp_2op_p_zds<0b0001, "fsub">;
+  defm FMUL_ZPmZ   : sve_fp_2op_p_zds<0b0010, "fmul">;
+  defm FSUBR_ZPmZ  : sve_fp_2op_p_zds<0b0011, "fsubr">;
+  defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">;
+  defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm">;
+  defm FMAX_ZPmZ   : sve_fp_2op_p_zds<0b0110, "fmax">;
+  defm FMIN_ZPmZ   : sve_fp_2op_p_zds<0b0111, "fmin">;
+  defm FABD_ZPmZ   : sve_fp_2op_p_zds<0b1000, "fabd">;
+  defm FSCALE_ZPmZ : sve_fp_2op_p_zds<0b1001, "fscale">;
+  defm FMULX_ZPmZ  : sve_fp_2op_p_zds<0b1010, "fmulx">;
+  defm FDIVR_ZPmZ  : sve_fp_2op_p_zds<0b1100, "fdivr">;
+  defm FDIV_ZPmZ   : sve_fp_2op_p_zds<0b1101, "fdiv">;
+
   defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
   defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">;
 

diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index 2c37be691bb2ce63022e78cc54b9684deb8b8eda..5be8ef1afd266d931bd616e95b48d67b8197cc0d 100644 (file)
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -958,6 +958,34 @@ multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
   def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
 }
 
+class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
+                       ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+  asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Zdn;
+  bits<5> Zm;
+  let Inst{31-24} = 0b01100101;
+  let Inst{23-22} = sz;
+  let Inst{21-20} = 0b00;
+  let Inst{19-16} = opc;
+  let Inst{15-13} = 0b100;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zm;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> {
+  def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
+  def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
+  def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
+}
+
+
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Multiply - Indexed Group
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/AArch64/SVE/fabd-diagnostics.s b/test/MC/AArch64/SVE/fabd-diagnostics.s
new file mode 100644 (file)
index 0000000..aadebc6
--- /dev/null
+++ b/test/MC/AArch64/SVE/fabd-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fabd    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fabd    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fabd    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fabd    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fabd    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fabd    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fabd    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fabd    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fabd.s b/test/MC/AArch64/SVE/fabd.s
new file mode 100644 (file)
index 0000000..98bbc50
--- /dev/null
+++ b/test/MC/AArch64/SVE/fabd.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fabd    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fabd    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x48,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 48 65 <unknown>
+
+fabd    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fabd    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x88,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 88 65 <unknown>
+
+fabd    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fabd    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c8 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fadd-diagnostics.s b/test/MC/AArch64/SVE/fadd-diagnostics.s
index 6af5aaf8f45dd26e149740c6fa0f2c462b1210ff..587e03fdd85df119b102c8e613ba6877acaaf05c 100644 (file)
--- a/test/MC/AArch64/SVE/fadd-diagnostics.s
+++ b/test/MC/AArch64/SVE/fadd-diagnostics.s
@@ -27,3 +27,35 @@ fadd z0.h, p0/m, z0.h, #0.9999999999999999999999999
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
 // CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.9999999999999999999999999
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fadd    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fadd    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fadd    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fadd    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fadd    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fadd    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fadd    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fadd.s b/test/MC/AArch64/SVE/fadd.s
index 4beed12b05e51f19dab4755da53ef514e434a604..238305d993fd4febcb1a810cdedda7ab861212f6 100644 (file)
--- a/test/MC/AArch64/SVE/fadd.s
+++ b/test/MC/AArch64/SVE/fadd.s
@@ -54,3 +54,21 @@ fadd    z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
+
+fadd    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fadd    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 40 65 <unknown>
+
+fadd    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fadd    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 80 65 <unknown>
+
+fadd    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fadd    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c0 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fdiv-diagnostics.s b/test/MC/AArch64/SVE/fdiv-diagnostics.s
new file mode 100644 (file)
index 0000000..48d8b69
--- /dev/null
+++ b/test/MC/AArch64/SVE/fdiv-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fdiv    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fdiv    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fdiv    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fdiv    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdiv    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fdiv    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fdiv    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fdiv    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fdiv.s b/test/MC/AArch64/SVE/fdiv.s
new file mode 100644 (file)
index 0000000..112d202
--- /dev/null
+++ b/test/MC/AArch64/SVE/fdiv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fdiv    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fdiv    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x4d,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 4d 65 <unknown>
+
+fdiv    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fdiv    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x8d,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 8d 65 <unknown>
+
+fdiv    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fdiv    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f cd 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fdivr-diagnostics.s b/test/MC/AArch64/SVE/fdivr-diagnostics.s
new file mode 100644 (file)
index 0000000..031d684
--- /dev/null
+++ b/test/MC/AArch64/SVE/fdivr-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fdivr    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fdivr    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fdivr    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fdivr    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdivr    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fdivr    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fdivr    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fdivr    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fdivr.s b/test/MC/AArch64/SVE/fdivr.s
new file mode 100644 (file)
index 0000000..3744dd9
--- /dev/null
+++ b/test/MC/AArch64/SVE/fdivr.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fdivr   z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fdivr   z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x4c,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 4c 65 <unknown>
+
+fdivr   z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fdivr   z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x8c,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 8c 65 <unknown>
+
+fdivr   z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fdivr   z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f cc 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fmax-diagnostics.s b/test/MC/AArch64/SVE/fmax-diagnostics.s
index ae0e6d04d3df4b6eb3f352e5d11de1db47b81032..e62aeb8247ca01d7eb9a84e66f3a457cd72c82e1 100644 (file)
--- a/test/MC/AArch64/SVE/fmax-diagnostics.s
+++ b/test/MC/AArch64/SVE/fmax-diagnostics.s
@@ -28,3 +28,34 @@ fmax z0.h, p0/m, z0.h, #0.9999999999999999999999999
 // CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.9999999999999999999999999
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fmax    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmax    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fmax    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmax    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmax    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmax    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmax    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fmax.s b/test/MC/AArch64/SVE/fmax.s
index 5e774d56e5a058c0debf81a71e47163948498fde..0e4a6d4c196e84261a083ef3c1b0e73eed7e6684 100644 (file)
--- a/test/MC/AArch64/SVE/fmax.s
+++ b/test/MC/AArch64/SVE/fmax.s
@@ -48,3 +48,21 @@ fmax    z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 80 de 65 <unknown>
+
+fmax    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fmax    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x46,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 46 65 <unknown>
+
+fmax    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fmax    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x86,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 86 65 <unknown>
+
+fmax    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fmax    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c6 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fmaxnm-diagnostics.s b/test/MC/AArch64/SVE/fmaxnm-diagnostics.s
new file mode 100644 (file)
index 0000000..467585a
--- /dev/null
+++ b/test/MC/AArch64/SVE/fmaxnm-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fmaxnm    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmaxnm    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fmaxnm    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxnm    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnm    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxnm    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmaxnm    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxnm    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fmaxnm.s b/test/MC/AArch64/SVE/fmaxnm.s
new file mode 100644 (file)
index 0000000..cc5143c
--- /dev/null
+++ b/test/MC/AArch64/SVE/fmaxnm.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxnm  z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fmaxnm  z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x44,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 44 65 <unknown>
+
+fmaxnm  z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fmaxnm  z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x84,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 84 65 <unknown>
+
+fmaxnm  z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fmaxnm  z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c4 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fmin-diagnostics.s b/test/MC/AArch64/SVE/fmin-diagnostics.s
new file mode 100644 (file)
index 0000000..7bf848a
--- /dev/null
+++ b/test/MC/AArch64/SVE/fmin-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fmin    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmin    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fmin    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmin    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmin    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmin    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmin    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmin    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fmin.s b/test/MC/AArch64/SVE/fmin.s
new file mode 100644 (file)
index 0000000..18c6cfb
--- /dev/null
+++ b/test/MC/AArch64/SVE/fmin.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmin    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fmin    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x47,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 47 65 <unknown>
+
+fmin    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fmin    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x87,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 87 65 <unknown>
+
+fmin    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fmin    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c7 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fminnm-diagnostics.s b/test/MC/AArch64/SVE/fminnm-diagnostics.s
new file mode 100644 (file)
index 0000000..1cd7b59
--- /dev/null
+++ b/test/MC/AArch64/SVE/fminnm-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fminnm    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fminnm    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fminnm    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminnm    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnm    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminnm    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fminnm    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminnm    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fminnm.s b/test/MC/AArch64/SVE/fminnm.s
new file mode 100644 (file)
index 0000000..a8d7472
--- /dev/null
+++ b/test/MC/AArch64/SVE/fminnm.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminnm  z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fminnm  z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x45,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 45 65 <unknown>
+
+fminnm  z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fminnm  z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x85,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 85 65 <unknown>
+
+fminnm  z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fminnm  z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c5 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fmul-diagnostics.s b/test/MC/AArch64/SVE/fmul-diagnostics.s
index 6b5ddc893fa533c3b745934685cf001dcf9c6097..2000b33df516c909157418cea3a2b9a88dd2a1f0 100644 (file)
--- a/test/MC/AArch64/SVE/fmul-diagnostics.s
+++ b/test/MC/AArch64/SVE/fmul-diagnostics.s
@@ -90,3 +90,35 @@ fmul z0.d, z0.d, z0.d[2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
 // CHECK-NEXT: fmul z0.d, z0.d, z0.d[2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fmul    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmul    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fmul    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmul    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmul    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmul    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmul    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fmul.s b/test/MC/AArch64/SVE/fmul.s
index 4f71cb5452a34b06ce682cf8e61de16f0a3611df..128be97e4c820f21234435e9a4a261bc0307b690 100644 (file)
--- a/test/MC/AArch64/SVE/fmul.s
+++ b/test/MC/AArch64/SVE/fmul.s
@@ -84,3 +84,21 @@ fmul    z31.d, z31.d, z15.d[1]
 // CHECK-ENCODING: [0xff,0x23,0xff,0x64]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 23 ff 64 <unknown>
+
+fmul    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fmul    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x42,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 42 65 <unknown>
+
+fmul    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fmul    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x82,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 82 65 <unknown>
+
+fmul    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fmul    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c2 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fmulx-diagnostics.s b/test/MC/AArch64/SVE/fmulx-diagnostics.s
new file mode 100644 (file)
index 0000000..9b0c6c9
--- /dev/null
+++ b/test/MC/AArch64/SVE/fmulx-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fmulx    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmulx    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fmulx    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmulx    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmulx    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmulx    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fmulx    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmulx    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fmulx.s b/test/MC/AArch64/SVE/fmulx.s
new file mode 100644 (file)
index 0000000..a1c8e6b
--- /dev/null
+++ b/test/MC/AArch64/SVE/fmulx.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmulx   z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fmulx   z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x4a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 4a 65 <unknown>
+
+fmulx   z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fmulx   z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x8a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 8a 65 <unknown>
+
+fmulx   z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fmulx   z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f ca 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fscale-diagnostics.s b/test/MC/AArch64/SVE/fscale-diagnostics.s
new file mode 100644 (file)
index 0000000..34a3c33
--- /dev/null
+++ b/test/MC/AArch64/SVE/fscale-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fscale    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fscale    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fscale    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fscale    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fscale    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fscale    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fscale    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fscale    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fscale.s b/test/MC/AArch64/SVE/fscale.s
new file mode 100644 (file)
index 0000000..0ce3d7e
--- /dev/null
+++ b/test/MC/AArch64/SVE/fscale.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fscale  z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fscale  z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x49,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 49 65 <unknown>
+
+fscale  z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fscale  z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x89,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 89 65 <unknown>
+
+fscale  z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fscale  z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c9 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fsub-diagnostics.s b/test/MC/AArch64/SVE/fsub-diagnostics.s
new file mode 100644 (file)
index 0000000..cb44c2a
--- /dev/null
+++ b/test/MC/AArch64/SVE/fsub-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fsub    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fsub    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fsub    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fsub    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsub    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fsub    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fsub    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fsub    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fsub.s b/test/MC/AArch64/SVE/fsub.s
new file mode 100644 (file)
index 0000000..e9e060f
--- /dev/null
+++ b/test/MC/AArch64/SVE/fsub.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fsub    z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fsub    z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 41 65 <unknown>
+
+fsub    z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fsub    z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 81 65 <unknown>
+
+fsub    z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fsub    z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c1 65 <unknown>

diff --git a/test/MC/AArch64/SVE/fsubr-diagnostics.s b/test/MC/AArch64/SVE/fsubr-diagnostics.s
new file mode 100644 (file)
index 0000000..c8ea652
--- /dev/null
+++ b/test/MC/AArch64/SVE/fsubr-diagnostics.s
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+fsubr    z0.h, p7/m, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fsubr    z0.h, p7/m, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+fsubr    z0.b, p7/m, z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fsubr    z0.b, p7/m, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsubr    z0.h, p7/m, z0.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fsubr    z0.h, p7/m, z0.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fsubr    z0.h, p8/m, z0.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fsubr    z0.h, p8/m, z0.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/fsubr.s b/test/MC/AArch64/SVE/fsubr.s
new file mode 100644 (file)
index 0000000..27ca019
--- /dev/null
+++ b/test/MC/AArch64/SVE/fsubr.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fsubr   z0.h, p7/m, z0.h, z31.h
+// CHECK-INST: fsubr   z0.h, p7/m, z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x9f,0x43,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 43 65 <unknown>
+
+fsubr   z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: fsubr   z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x9f,0x83,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f 83 65 <unknown>
+
+fsubr   z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: fsubr   z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 9f c3 65 <unknown>